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Searched +full:usb +full:- +full:dc +full:- +full:cal (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c76 * For usb offload solution, some USB registers must be tuned
121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers()
227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers()
238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
242 extoff = -1; in ar9300_get_channel_centers()
245 centers->ctl_center = in ar9300_get_channel_centers()
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H A Dar9300phy.h17 * Copyright (c) 2002-2005 Atheros Communications, Inc.
280 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction…
393 #define AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ -110
394 #define AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ -115
395 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ -125
396 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ -125
397 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ -95
398 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ -100
399 #define AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ -105
401 #define AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ -127
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/freebsd/share/misc/
H A Dusb_vendors2 # List of USB ID's
4 # Maintained by Stephen J. Gowdy <linux.usb.ids@gmail.com>
6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2025-09-15 20:34:02
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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