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/linux/Documentation/devicetree/bindings/serial/
H A Datmel,at91-usart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
11 - Richard Genoud <richard.genoud@bootlin.com>
16 - enum:
17 - atmel,at91rm9200-usart
18 - atmel,at91sam9260-usart
19 - items:
[all …]
/linux/drivers/mfd/
H A Dat91-usart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for AT91 USART
11 #include <dt-bindings/mfd/at91-usart.h>
29 device_property_read_u32(&pdev->dev, "atmel,usart-mode", &opmode); in at91_usart_mode_probe()
39 dev_err(&pdev->dev, "atmel,usart-mode has an invalid value %u\n", in at91_usart_mode_probe()
41 return -EINVAL; in at91_usart_mode_probe()
44 return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, cell, 1, in at91_usart_mode_probe()
49 { .compatible = "atmel,at91rm9200-usart" },
50 { .compatible = "atmel,at91sam9260-usart" },
67 MODULE_DESCRIPTION("AT91 USART MFD driver");
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_uart.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
24 pinctrl_uart0: uart0-0 {
32 pinctrl_uart1: uart1-0 {
41 compatible = "atmel,at91sam9260-usart";
43 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
[all …]
H A Dat91sam9260.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
7 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dat91rm9200.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
[all …]
H A Dat91sam9x5_usart3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
4 * 4 USART.
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mfd/at91-usart.h>
22 pinctrl_usart3: usart3-0 {
28 pinctrl_usart3_rts: usart3_rts-0 {
33 pinctrl_usart3_cts: usart3_cts-0 {
38 pinctrl_usart3_sck: usart3_sck-0 {
[all …]
H A Dat91sam9x5.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dat91sam9rl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
[all …]
H A Dat91sam9n12.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dat91sam9261.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 #include <dt-bindings/pinctrl/at91.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dsama5d4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
9 #include <dt-bindings/clock/at91.h>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/mfd/at91-usart.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dsama5d3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
H A Dat91sam9g45.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dat91sam9263.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <dt-bindings/pinctrl/at91.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
H A Dat91-ariag25.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
8 /dts-v1/;
32 clock-frequency = <32768>;
36 clock-frequency = <12000000>;
41 compatible = "gpio-leds";
47 linux,default-trigger = "heartbeat";
53 compatible = "w1-gpio";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_w1_0>;
[all …]
H A Dat91-sam9x60_curiosity.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
15 compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
24 stdout-path = "serial0:115200n8";
33 clock-frequency = <32768>;
37 clock-frequency = <24000000>;
41 gpio-keys {
42 compatible = "gpio-keys";
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Datmel,sama5d2-flexcom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
14 an I2C controller and an USART. Only one function can be used at a
20 - const: atmel,sama5d2-flexcom
21 - items:
22 - const: microchip,sam9x7-flexcom
23 - const: atmel,sama5d2-flexcom
[all …]
/linux/drivers/tty/serial/
H A Datmel_serial.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * USART registers.
27 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
31 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
42 #define ATMEL_US_MR 0x04 /* Mode Register */
43 #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */
62 #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */
75 #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */
81 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
83 #define ATMEL_US_OVER BIT(19) /* Oversampling Mode */
[all …]
H A Dstm32-usart.c1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
16 #include <linux/dma-direction.h>
18 #include <linux/dma-mapping.h>
37 #include "stm32-usart.h"
124 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
126 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
133 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
135 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
141 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
[all …]
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
146 * value is 0x3 (31 bit-time).
[all …]
/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
[all …]
/linux/Documentation/driver-api/surface_aggregator/
H A Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0+
10 its responsibilities and feature-set have since been expanded significantly
23 sensors (e.g. skin temperature) and cooling/performance-mode setting to the
36 SAN), translating ACPI generic serial bus write-/read-accesses to SAM
40 harder to discover and requiring us to hard-code a sort of device registry.
50 communicate via HID, specifically using a HID-over-I2C device, whereas on
51 5th and later generations, communication takes place via a USART serial
55 SAM-over-SSH and SAM-over-HID.
57 Currently, this subsystem only supports SAM-over-SSH. The SSH communication
64 ------------------
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
16 #include <linux/dma-mapping.h>
31 #include "../virt-dma.h"
42 #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
49 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
64 #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */
66 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
68 #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
[all …]
/linux/drivers/dma/
H A Dat_xdmac.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/dma/at91.h>
141 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
216 /* ----- Channels ----- */
241 /* ----- Controller ----- */
256 /* ----- Descriptors ----- */
271 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
312 return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40); in at_xdmac_chan_reg_base()
315 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
[all …]

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