xref: /linux/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml (revision f66bc387efbee59978e076ce9bf123ac353b389c) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,qcs615-ufshc
30          - qcom,qcs8300-ufshc
31          - qcom,sa8775p-ufshc
32          - qcom,sc7180-ufshc
33          - qcom,sc7280-ufshc
34          - qcom,sc8180x-ufshc
35          - qcom,sc8280xp-ufshc
36          - qcom,sdm845-ufshc
37          - qcom,sm6115-ufshc
38          - qcom,sm6125-ufshc
39          - qcom,sm6350-ufshc
40          - qcom,sm8150-ufshc
41          - qcom,sm8250-ufshc
42          - qcom,sm8350-ufshc
43          - qcom,sm8450-ufshc
44          - qcom,sm8550-ufshc
45          - qcom,sm8650-ufshc
46          - qcom,sm8750-ufshc
47      - const: qcom,ufshc
48      - const: jedec,ufs-2.0
49
50  clocks:
51    minItems: 7
52    maxItems: 9
53
54  clock-names:
55    minItems: 7
56    maxItems: 9
57
58  dma-coherent: true
59
60  interconnects:
61    minItems: 2
62    maxItems: 2
63
64  interconnect-names:
65    items:
66      - const: ufs-ddr
67      - const: cpu-ufs
68
69  iommus:
70    minItems: 1
71    maxItems: 2
72
73  phys:
74    maxItems: 1
75
76  phy-names:
77    items:
78      - const: ufsphy
79
80  power-domains:
81    maxItems: 1
82
83  qcom,ice:
84    $ref: /schemas/types.yaml#/definitions/phandle
85    description: phandle to the Inline Crypto Engine node
86
87  reg:
88    minItems: 1
89    maxItems: 2
90
91  reg-names:
92    items:
93      - const: std
94      - const: ice
95
96  required-opps:
97    maxItems: 1
98
99  resets:
100    maxItems: 1
101
102  '#reset-cells':
103    const: 1
104
105  reset-names:
106    items:
107      - const: rst
108
109  reset-gpios:
110    maxItems: 1
111    description:
112      GPIO connected to the RESET pin of the UFS memory device.
113
114required:
115  - compatible
116  - reg
117
118allOf:
119  - $ref: ufs-common.yaml
120
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - qcom,sc7180-ufshc
127    then:
128      properties:
129        clocks:
130          minItems: 7
131          maxItems: 7
132        clock-names:
133          items:
134            - const: core_clk
135            - const: bus_aggr_clk
136            - const: iface_clk
137            - const: core_clk_unipro
138            - const: ref_clk
139            - const: tx_lane0_sync_clk
140            - const: rx_lane0_sync_clk
141        reg:
142          maxItems: 1
143        reg-names:
144          maxItems: 1
145
146  - if:
147      properties:
148        compatible:
149          contains:
150            enum:
151              - qcom,msm8998-ufshc
152              - qcom,qcs8300-ufshc
153              - qcom,sa8775p-ufshc
154              - qcom,sc7280-ufshc
155              - qcom,sc8180x-ufshc
156              - qcom,sc8280xp-ufshc
157              - qcom,sm8250-ufshc
158              - qcom,sm8350-ufshc
159              - qcom,sm8450-ufshc
160              - qcom,sm8550-ufshc
161              - qcom,sm8650-ufshc
162              - qcom,sm8750-ufshc
163    then:
164      properties:
165        clocks:
166          minItems: 8
167          maxItems: 8
168        clock-names:
169          items:
170            - const: core_clk
171            - const: bus_aggr_clk
172            - const: iface_clk
173            - const: core_clk_unipro
174            - const: ref_clk
175            - const: tx_lane0_sync_clk
176            - const: rx_lane0_sync_clk
177            - const: rx_lane1_sync_clk
178        reg:
179          minItems: 1
180          maxItems: 1
181        reg-names:
182          maxItems: 1
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - qcom,sdm845-ufshc
190              - qcom,sm6350-ufshc
191              - qcom,sm8150-ufshc
192    then:
193      properties:
194        clocks:
195          minItems: 9
196          maxItems: 9
197        clock-names:
198          items:
199            - const: core_clk
200            - const: bus_aggr_clk
201            - const: iface_clk
202            - const: core_clk_unipro
203            - const: ref_clk
204            - const: tx_lane0_sync_clk
205            - const: rx_lane0_sync_clk
206            - const: rx_lane1_sync_clk
207            - const: ice_core_clk
208        reg:
209          minItems: 2
210          maxItems: 2
211        reg-names:
212          minItems: 2
213      required:
214        - reg-names
215
216  - if:
217      properties:
218        compatible:
219          contains:
220            enum:
221              - qcom,msm8996-ufshc
222    then:
223      properties:
224        clocks:
225          minItems: 9
226          maxItems: 9
227        clock-names:
228          items:
229            - const: core_clk
230            - const: bus_clk
231            - const: bus_aggr_clk
232            - const: iface_clk
233            - const: core_clk_unipro
234            - const: core_clk_ice
235            - const: ref_clk
236            - const: tx_lane0_sync_clk
237            - const: rx_lane0_sync_clk
238        reg:
239          minItems: 1
240          maxItems: 1
241        reg-names:
242          maxItems: 1
243
244  - if:
245      properties:
246        compatible:
247          contains:
248            enum:
249              - qcom,qcs615-ufshc
250              - qcom,sm6115-ufshc
251              - qcom,sm6125-ufshc
252    then:
253      properties:
254        clocks:
255          minItems: 8
256          maxItems: 8
257        clock-names:
258          items:
259            - const: core_clk
260            - const: bus_aggr_clk
261            - const: iface_clk
262            - const: core_clk_unipro
263            - const: ref_clk
264            - const: tx_lane0_sync_clk
265            - const: rx_lane0_sync_clk
266            - const: ice_core_clk
267        reg:
268          minItems: 2
269          maxItems: 2
270        reg-names:
271          minItems: 2
272      required:
273        - reg-names
274
275    # TODO: define clock bindings for qcom,msm8994-ufshc
276
277  - if:
278      required:
279        - qcom,ice
280    then:
281      properties:
282        reg:
283          maxItems: 1
284        clocks:
285          minItems: 7
286          maxItems: 8
287    else:
288      properties:
289        reg:
290          minItems: 1
291          maxItems: 2
292        clocks:
293          minItems: 7
294          maxItems: 9
295
296unevaluatedProperties: false
297
298examples:
299  - |
300    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
301    #include <dt-bindings/clock/qcom,rpmh.h>
302    #include <dt-bindings/gpio/gpio.h>
303    #include <dt-bindings/interconnect/qcom,sm8450.h>
304    #include <dt-bindings/interrupt-controller/arm-gic.h>
305
306    soc {
307        #address-cells = <2>;
308        #size-cells = <2>;
309
310        ufs@1d84000 {
311            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
312                         "jedec,ufs-2.0";
313            reg = <0 0x01d84000 0 0x3000>;
314            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
315            phys = <&ufs_mem_phy_lanes>;
316            phy-names = "ufsphy";
317            lanes-per-direction = <2>;
318            #reset-cells = <1>;
319            resets = <&gcc GCC_UFS_PHY_BCR>;
320            reset-names = "rst";
321            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
322
323            vcc-supply = <&vreg_l7b_2p5>;
324            vcc-max-microamp = <1100000>;
325            vccq-supply = <&vreg_l9b_1p2>;
326            vccq-max-microamp = <1200000>;
327
328            power-domains = <&gcc UFS_PHY_GDSC>;
329            iommus = <&apps_smmu 0xe0 0x0>;
330            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
331                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
332            interconnect-names = "ufs-ddr", "cpu-ufs";
333
334            clock-names = "core_clk",
335                          "bus_aggr_clk",
336                          "iface_clk",
337                          "core_clk_unipro",
338                          "ref_clk",
339                          "tx_lane0_sync_clk",
340                          "rx_lane0_sync_clk",
341                          "rx_lane1_sync_clk";
342            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
343                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
344                     <&gcc GCC_UFS_PHY_AHB_CLK>,
345                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
346                     <&rpmhcc RPMH_CXO_CLK>,
347                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
348                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
349                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
350            freq-table-hz = <75000000 300000000>,
351                            <0 0>,
352                            <0 0>,
353                            <75000000 300000000>,
354                            <75000000 300000000>,
355                            <0 0>,
356                            <0 0>,
357                            <0 0>;
358            qcom,ice = <&ice>;
359        };
360    };
361