Searched +full:uart11 +full:- +full:pins (Results 1 – 10 of 10) sorted by relevance
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/ |
H A D | ma35d1-som-256m.dts | 1 // SPDX-License-Identifier: GPL-2.0 4 * Author: Shan-Chun Hung <schung@nuvoton.com> 8 /dts-v1/; 12 model = "Nuvoton MA35D1-SOM"; 13 compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; 17 serial11 = &uart11; 24 stdout-path = "serial0:115200n8"; 32 clk_hxt: clock-hxt { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | aspeed,ast2600-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Jeffery <andrew@aj.id.au> 16 - compatible: Should be one of the following: 17 "aspeed,ast2600-scu", "syscon", "simple-mfd" 29 const: aspeed,ast2600-pinctrl 32 $ref: pinmux-node.yaml# 38 - ADC0 [all …]
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H A D | nuvoton,ma35d1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shan-Chun Hung <schung@nuvoton.com> 11 - Jacky Huang <ychuang3@nuvoton.com> 14 - $ref: pinctrl.yaml# 19 - nuvoton,ma35d1-pinctrl 24 '#address-cells': 27 '#size-cells': [all …]
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H A D | bitmain,bm1880-pinctrl.txt | 7 - compatible: Should be "bitmain,bm1880-pinctrl" 8 - reg: Offset and length of pinctrl space in SCTRL. 10 Please refer to pinctrl-bindings.txt in this directory for details of the 16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC 17 includes pinmux and various pin configuration parameters, such as pull-up, 24 The following generic properties as defined in pinctrl-bindings.txt are valid 29 - pins: An array of strings, each string containing the name of a pin. 30 Valid values for pins are: 32 MIO0 - MIO111 34 - groups: An array of strings, each string containing the name of a pin [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
H A D | exynosautov9-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source 7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as 11 #include "exynos-pinctrl.h" 14 gpa0: gpa0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 17 interrupt-controller; 18 #interrupt-cells = <2>; 19 interrupt-parent = <&gic>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | sc7280.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 7 #include <dt-bindings/clock/qcom,camcc-sc7280.h> 8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13 #include <dt-bindings/clock/qcom,rpmh.h> 14 #include <dt-bindings/clock/qcom,videocc-sc7280.h> [all …]
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H A D | sc7180.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h> 14 #include <dt-bindings/firmware/qcom,scm.h> 15 #include <dt-bindings/interconnect/qcom,icc.h> [all …]
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H A D | sdm845.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h> 13 #include <dt-bindings/clock/qcom,rpmh.h> 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h> 15 #include <dt-bindings/dma/qcom-gpi.h> 16 #include <dt-bindings/firmware/qcom,scm.h> [all …]
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/freebsd/sys/contrib/device-tree/src/arm/st/ |
H A D | stih407-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include "st-pincfg.h" 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 /* 0-5: PIO_SBC */ 18 /* 10-19: PIO_FRONT0 */ 31 /* 30-35: PIO_REAR */ 38 /* 40-42: PIO_FLASH */ 45 pin-controller-sbc@961f080 { 46 #address-cells = <1>; 47 #size-cells = <1>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/ |
H A D | gs101-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * GS101 SoC pin-mux and pin-config device tree source 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 9 #include "gs101-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 15 interrupt-controller; 16 #interrupt-cells = <2>; [all …]
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