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/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_uart.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
16 serial5 = &uart0;
23 uart0 {
24 pinctrl_uart0: uart0-0 {
32 pinctrl_uart1: uart1-0 {
[all …]
H A Dat91-ariag25.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
8 /dts-v1/;
17 serial5 = &uart0;
32 clock-frequency = <32768>;
36 clock-frequency = <12000000>;
41 compatible = "gpio-leds";
47 linux,default-trigger = "heartbeat";
53 compatible = "w1-gpio";
55 pinctrl-names = "default";
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am6548-iot2050-advanced-sm.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2
11 * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
14 * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
17 /dts-v1/;
19 #include "k3-am6548-iot2050-advanced-common.dtsi"
20 #include "k3-am65-iot2050-common-pg2.dtsi"
23 compatible = "siemens,iot2050-advanced-sm", "ti,am654";
38 pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>;
40 led-2 {
[all …]
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
14 "default",
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
[all …]
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-iot-512m.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 /dts-v1/;
12 model = "Nuvoton MA35D1-IoT";
13 compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
16 serial0 = &uart0;
24 stdout-path = "serial0:115200n8";
32 clk_hxt: clock-hxt {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
[all …]
H A Dma35d1-som-256m.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 /dts-v1/;
12 model = "Nuvoton MA35D1-SOM";
13 compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
16 serial0 = &uart0;
24 stdout-path = "serial0:115200n8";
32 clk_hxt: clock-hxt {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
[all …]
H A Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880-sophon-edge.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
19 * Line names are taken from the schematic "sophon-edge-schematics"
29 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
34 compatible = "bitmain,sophon-edge", "bitmain,bm1880";
38 serial0 = &uart0;
44 stdout-path = "serial0:115200n8";
54 porta: gpio-controller@0 {
55 gpio-line-names =
56 "GPIO-A", /* GPIO0, LSEC pin 23 */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dimg,pistachio-pinctrl.txt8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
22 - gpio-controller: Indicates the device is a GPIO controller.
[all …]
H A Daxis,artpec6-pinctrl.txt1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
37 uart0: uart0grp0, uart0grp1, uart0grp2
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
[all …]
H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl",
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
14 serial0 = &uart0;
18 stdout-path = "serial0:921600n8";
32 pinctrl-names = "default";
33 pinctrl-0 = <&i2c0_pin>;
34 clock-frequency = <100000>;
39 pinctrl-names = "default";
40 pinctrl-0 = <&i2c1_pin>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-s8815.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik S8815 board
7 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include "ste-nomadik-stn8815.dtsi"
12 model = "Calao Systems USB-S8815";
13 compatible = "calaosystems,usb-s8815";
20 serial0 = &uart0;
26 mmcsd-gpio {
27 gpio-hog;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200-poplar.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
12 #include "poplar-pinctrl.dtsi"
16 compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
19 serial0 = &uart0;
24 stdout-path = "serial0:115200n8";
33 compatible = "gpio-leds";
35 user-led0 {
[all …]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
26 /dts-v1/;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-chiliboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
6 /dts-v1/;
7 #include "am335x-chilisom.dtsi"
11 compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
15 stdout-path = &uart0;
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_gpio_pins>;
26 default-state = "keep";
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
27 serial0 = &uart0;
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-openblocks_a6.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
9 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
18 stdout-path = &uart0;
31 nr-ports = <1>;
44 pinctrl: pin-controller@10000 {
45 pinctrl-0 = <&pmx_dip_switches>;
46 pinctrl-names = "default";
48 pmx_uart0: pmx-uart0 {
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
16 serial0 = &uart0;
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520-lichee-pi-4a.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "th1520-lichee-module-4a.dtsi"
10 compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
19 serial0 = &uart0;
29 stdout-path = "serial0:115200n8";
34 uart0_pins: uart0-0 {
35 tx-pins {
38 bias-disable;
39 drive-strength = <3>;
40 input-disable;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
14 serial0 = &uart0;
18 stdout-path = "serial0:115200n8";
22 &uart0 {
24 * UART0 is available on two ports: PB and PF, both are accessible.
[all …]
H A Dsuniv-f1c200s-popstick-v1.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "suniv-f1c100s.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
15 "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
18 serial0 = &uart0;
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
[all …]

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