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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
[all …]
H A Dimg,pistachio-pinctrl.txt8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
22 - gpio-controller: Indicates the device is a GPIO controller.
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
16 mpp0 0 gpio, uart0(rxd)
17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
24 mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
26 mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
[all …]
H A Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
[all …]
H A Draspberrypi,rp1-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A. della Porta <andrea.porta@suse.com>
14 sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped
20 const: raspberrypi,rp1-gpio
26 '#gpio-cells':
28 to specify the flags (see include/dt-bindings/gpio/gpio.h).
31 gpio-controller: true
[all …]
H A Daxis,artpec6-pinctrl.txt1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
37 uart0: uart0grp0, uart0grp1, uart0grp2
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
[all …]
H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
14 SYSTEM CONTROLLER 0
18 -----
[all...]
/freebsd/sys/dts/arm/
H A Dversatilepb.dts3 /dts-v1/;
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "arm,versatile-pb";
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 intc: interrupt-controller {
18 compatible = "arm,versatile-vic";
19 reg = <0x10140000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama5d3_uart.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
16 serial5 = &uart0;
23 uart0 {
24 pinctrl_uart0: uart0-0 {
32 pinctrl_uart1: uart1-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2002-licheerv-nano-b.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
19 serial0 = &uart0;
27 stdout-path = "serial0:115200n8";
32 clock-frequency = <25000000>;
36 uart0_cfg: uart0-cfg {
37 uart0-pins {
38 pinmux = <PINMUX(PIN_UART0_TX, 0)>,
39 <PINMUX(PIN_UART0_RX, 0)>;
[all …]
H A Dcv1800b-milkv-duo.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 model = "Milk-V Duo";
15 serial0 = &uart0;
23 stdout-path = "serial0:115200n8";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
32 reg = <0x83f40000 0xc0000>;
33 no-map;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm283x.dtsi1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
11 /memreserve/ 0x00000000 0x00001000;
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
[all …]
H A Dk3-am6548-iot2050-advanced-sm.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2
11 * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
14 * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
17 /dts-v1/;
19 #include "k3-am6548-iot2050-advanced-common.dtsi"
20 #include "k3-am65-iot2050-common-pg2.dtsi"
23 compatible = "siemens,iot2050-advanced-sm", "ti,am654";
29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
30 <0x00000008 0x80000000 0x00000000 0x80000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520-lichee-pi-4a.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "th1520-lichee-module-4a.dtsi"
10 compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
19 serial0 = &uart0;
29 stdout-path = "serial0:115200n8";
34 uart0_pins: uart0-0 {
35 tx-pins {
38 bias-disable;
39 drive-strength = <3>;
40 input-disable;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
14 serial0 = &uart0;
18 stdout-path = "serial0:115200n8";
22 &uart0 {
24 * UART0 is available on two ports: PB and PF, both are accessible.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/sophgo/
H A Dsg2000-milkv-duo-module-01-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "sg2000-milkv-duo-module-01.dtsi"
8 model = "Milk-V Duo Module 01 Evaluation Board";
9 compatible = "milkv,duo-module-01-evb", "milkv,duo-module-01", "sophgo,sg2000";
12 stdout-path = "serial0:115200n8";
17 sdhci0_cfg: sdhci0-cfg {
18 sdhci0-cd-pins {
19 pinmux = <PINMUX(PIN_SD0_CD, 0)>;
20 bias-pull-up;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dsd5203.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
13 interrupt-parent = <&vic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
22 serial0 = &uart0;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,arm926ej-s";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
38 reg = <0x28000000 0x800000>; /* 8 MB */
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,s5pv210-clock.txt9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
27 clock-output-names:
28 - "xxti": external crystal oscillator connected to XXTI and XXTO pins of
30 - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
34 board device tree, including the system base clock, as selected by XOM[0]
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm3384_viper.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
7 memory@0 {
11 reg = <0x06000000 0x02000000>,
12 <0x0e000000 0x02000000>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 mips-hpt-frequency = <300000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dma35d1-som-256m.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 /dts-v1/;
12 model = "Nuvoton MA35D1-SOM";
13 compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
16 serial0 = &uart0;
24 stdout-path = "serial0:115200n8";
29 reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
32 clk_hxt: clock-hxt {
33 compatible = "fixed-clock";
[all …]
H A Dma35d1-iot-512m.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 /dts-v1/;
12 model = "Nuvoton MA35D1-IoT";
13 compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
16 serial0 = &uart0;
24 stdout-path = "serial0:115200n8";
29 reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
32 clk_hxt: clock-hxt {
33 compatible = "fixed-clock";
[all …]

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