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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie.txt4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible:
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
14 - interrupts: A list of interrupt outputs of the controller. Must contain an
15 entry for each entry in the interrupt-names property.
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H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - fsl,imx8mq-usb-phy
16 - fsl,imx8mp-usb-phy
21 "#phy-cells":
27 clock-names:
29 - const: phy
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-var-dart.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Support for Variscite DART-MX6 Module
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/fsl-imx-audmux.h>
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
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H A Dimx6q-ba16.dtsi2 * Support for imx6 based Advantech DMS-BA16 Qseven module
7 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/gpio/gpio.h>
55 compatible = "pwm-backlight";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_display>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
85 default-brightness-level = <255>;
86 enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
89 reg_1p8v: regulator-1p8v {
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/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_chan.c1 /*-
67 /* Write per-MCS Tx power. */ in r12a_write_txpower_ht()
78 if (sc->ntxchains >= 2) { in r12a_write_txpower_ht()
91 /* TODO: HT MCS 16 -> 31 */ in r12a_write_txpower_ht()
114 if (sc->ntxchains == 1) { in r12a_write_txpower_vht()
129 if (sc->ntxchains > 1) { in r12a_write_txpower_vht()
138 if (sc->ntxchains > 1) { in r12a_write_txpower_vht()
156 /* Write per-CCK rate Tx power. */ in r12a_write_txpower_cck()
170 /* Write per-OFDM rate Tx power. */ in r12a_write_txpower_ofdm()
196 power_level -= 10; in r12a_tx_power_training()
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
108 * Loops back the TX serializer output into the CDR.
114 * Loops back the TX driver IO signal to the RX IO pins
129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
197 * maximum swing of the driver.
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H A Dal_hal_pcie.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
57 * - Interrupt Handling.
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H A Dal_hal_pcie.c1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
72 /** RC - Revisions 1/2 */
77 /** EP - Revisions 1/2 */
82 /** RC - Revision 3 */
87 /** EP - Revision 3 */
96 #define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \
113 al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en, in al_pcie_port_wr_to_ro_set()
131 (pcie_port->rev_id == AL_PCIE_REV_ID_3) ? 0x4000 : 0x1000; in al_reg_write32_dbi_cs2()
154 struct al_pcie_regs *regs = pcie_port->regs; in al_pcie_port_link_speed_ctrl_set()
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
73 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
76 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
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/freebsd/contrib/sqlite3/
H A Dsqlite3.c17 ** language. The code for the "sqlite3" command-line shell is also in a
20 ** The content in this amalgamation comes from Fossil check-in
51 ** NO_TEST - The branches on this line are not
56 ** OPTIMIZATION-IF-TRUE - This branch is allowed to always be false
60 ** OPTIMIZATION-IF-FALSE - This branch is allowed to always be true
64 ** PREVENTS-HARMLESS-OVERREAD - This branch prevents a buffer overread
69 ** slash-asterisk...asterisk-slash comment marks, with no spaces between the
144 ** 2015-03-02
182 ** large file support, or if the OS is windows, these should be no-ops.
188 ** Large file support can be disabled using the -DSQLITE_DISABLE_LFS switch
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