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/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include "mlxbf-tmfifo-regs.h"
26 /* Vring size. */
29 /* Console Tx buffer size. */
32 /* Console Tx buffer reserved space. */
35 /* House-keeping timer interval. */
38 /* Virtual devices sharing the TM FIFO. */
50 /* Tx timeout in milliseconds. */
53 /* ACPI UID for BlueField-3. */
59 * struct mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
[all …]
/linux/drivers/net/ethernet/google/gve/
H A Dgve_tx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
20 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
26 struct gve_tx_ring *tx = &priv->tx[tx_qid]; in gve_xdp_tx_flush() local
28 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_tx_flush()
32 * We copy skb payloads into the registered segment before writing Tx
33 * descriptors and ringing the Tx doorbell.
35 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
39 static int gve_tx_fifo_init(struct gve_priv *priv, struct gve_tx_fifo *fifo) in gve_tx_fifo_init() argument
41 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
H A Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
[all …]
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_mbx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
8 * @fifo: pointer to FIFO
9 * @buffer: pointer to memory to be used to store FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
12 static void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size) in fm10k_fifo_init() argument
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5121-psc.txt4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsam9x60.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
[all …]
H A Dsama5d2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 interrupt-parent = <&aic>;
[all …]
H A Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define GLOB_PSIZE 0x08UL /* Packet Size */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
34 #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
35 #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
36 #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
37 #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
45 /* The following registers are for per-qe channel information/status. */
[all …]
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
[all …]
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
54 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
57 * DEFAULT: 0x0, SIZE: 1 bit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxpci.h4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
45 #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46 #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47 #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48 #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49 #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50 #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51 #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52 #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53 #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-ram.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
9 #include "mcp251xfd-ram.h"
17 max = min_t(u8, obj->max, obj->fifo_num * config->fifo_depth); in can_ram_clamp()
18 return clamp(val, obj->min, max); in can_ram_clamp()
26 u8 fifo_num = obj->fifo_num; in can_ram_rounddown_pow_of_two()
32 /* Use 1st FIFO for coalescing, if requested. in can_ram_rounddown_pow_of_two()
34 * Either use complete FIFO (and FIFO Full IRQ) for in can_ram_rounddown_pow_of_two()
35 * coalescing or only half of FIFO (FIFO Half Full in can_ram_rounddown_pow_of_two()
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
13 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
14 * info about buffer's location, size and ID. An ID field is used to identify a
15 * buffer when it's returned with data via RXD Fifo (see below)
16 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
18 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
20 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
23 * One holds 1.5K packets and another - 26K packets. Depending on incoming
24 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
/linux/drivers/i2c/busses/
H A Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
78 /* Most significant word offset in FIFO port */
151 /* TAG length for DATA READ in RX FIFO */
163 * tx_tag_len: tx tag length for current block
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
169 * tx_fifo_data_pos: current byte number in TX FIFO word
171 * rx_fifo_data_pos: current byte number in RX FIFO word
172 * fifo_available: number of available bytes in RX FIFO for current
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
[all …]
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
/linux/drivers/rpmsg/
H A Dqcom_glink_rpm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
27 #define RPM_TOC_MAX_ENTRIES ((RPM_TOC_SIZE - sizeof(struct rpm_toc)) / \
38 __le32 size; member
54 void __iomem *fifo; member
75 head = readl(pipe->head); in glink_rpm_rx_avail()
76 tail = readl(pipe->tail); in glink_rpm_rx_avail()
79 return pipe->native.length - tail + head; in glink_rpm_rx_avail()
81 return head - tail; in glink_rpm_rx_avail()
91 tail = readl(pipe->tail); in glink_rpm_rx_peek()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm283x-rpi-usb-otg.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
8 * fifo sizes shouldn't exceed 3776 bytes.
10 g-tx-fifo-size = <256 256 512 512 512 768 768>;

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