Home
last modified time | relevance | path

Searched +full:tx +full:- +full:clk +full:- +full:delay +full:- +full:ps (Results 1 – 25 of 53) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
21 interface and timing delay.
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwma
[all...]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/dev/mii/
H A Dmcommphy.c98 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
141 * different TX inverted configuration depending on speed used in mcommphy_service()
143 if (sc->mii_mpd_model == MCOMMPHY_YT8531_MODEL && in mcommphy_service()
144 (sc->mii_media_active != mii->mii_media_active || in mcommphy_service()
145 sc->mii_media_status != mii->mii_media_status)) { in mcommphy_service()
170 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MCOMMPHY_YT8511_OUI && in mcommphy_probe()
171 MII_MODEL(ma->mii_id2) == MCOMMPHY_YT8511_MODEL && in mcommphy_probe()
172 MII_REV(ma->mii_id2) == MCOMMPHY_YT8511_REV) { in mcommphy_probe()
192 if (sc->mii_flags & MIIF_RX_DELAY) { in mcommphy_yt8511_setup()
198 if (sc->mii_flags & MIIF_TX_DELAY) { in mcommphy_yt8511_setup()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779a0-falcon.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
8 /dts-v1/;
9 #include "r8a779a0-falcon-cpu.dtsi"
10 #include "r8a779a0-falcon-csi-dsi.dtsi"
11 #include "r8a779a0-falcon-ethernet.dtsi"
15 compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
23 pinctrl-0 = <&avb0_pins>;
24 pinctrl-names = "default";
25 phy-handle = <&phy0>;
[all …]
H A Dr8a779h0.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
8 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 /* External Audio clock - to be overridden by boards that provide it */
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
H A Dwhite-hawk-cpu-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
27 stdout-path = "serial0:921600n8";
30 sn65dsi86_refclk: clk-x6 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
37 compatible = "gpio-keys";
[all …]
H A Dr8a779h0-gray-hawk-single.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4M Gray Hawk Single board
11 * Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
28 /dts-v1/;
30 #include <dt-bindings/gpio/gpio.h>
31 #include <dt-bindings/input/input.h>
32 #include <dt-bindings/leds/common.h>
38 compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
50 can_transceiver0: can-phy0 {
52 #phy-cells = <0>;
[all …]
H A Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
13 model = "Renesas R-Car Gen3 ULCB board";
32 stdout-path = "serial0:115200n8";
35 audio_clkout: audio-clkout {
38 * but needed to avoid cs2000/rcar_sound probe dead-loc
[all...]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Dam335x-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "ti,am335x-evm", "ti,am33xx";
16 cpu0-supply = <&vdd1_reg>;
26 stdout-path = &uart0;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
[all …]
H A Dam335x-cm-t335.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335
5 * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "CompuLab CM-T335";
15 compatible = "compulab,cm-t335", "ti,am33xx";
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&gpio_led_pins>;
[all …]
/freebsd/sys/arm/allwinner/
H A Dif_awg.c1 /*-
62 #include <dev/clk/clk.h>
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h618-orangepi-zero3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
17 cpu-supply = <&reg_dcdc2>;
21 allwinner,tx-delay-ps = <700>;
22 phy-mode = "rgmii-rxid";
23 phy-supply = <&reg_dldo1>;
27 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
H A Dsun50i-h6-pine-h64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
22 stdout-path = "serial0:115200n8";
25 ext_osc32k: ext-osc32k-clk {
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
24 stdout-path = &lpuart0;
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
30 mbox-names = "tx", "rx", "rxdb";
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
[all …]
H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
H A Dimx8qm-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 /dts-v1/;
9 #include <dt-bindings/usb/pd.h>
14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
17 stdout-path = &lpuart0;
21 /delete-node/ cpu-map;
22 /delete-node/ cpu@100;
23 /delete-node/ cpu@101;
26 thermal-zones {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-ce
[all...]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
44 #define AR_TXCFG 0x0030 /* TX configuration register */
49 #define AR_TXNOFRM 0x004c /* TX no frame timeout register */
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
[all …]

123