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Searched +full:tx +full:- +full:amplitude +full:- +full:100 +full:base +full:- +full:tx +full:- +full:percent (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/net/phy/
H A Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
152 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */
155 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */
157 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */
159 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */
215 struct net_device *ndev = phydev->attached_dev; in dp83822_config_wol()
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_config_wol()
220 mac = (const u8 *)ndev->dev_addr; in dp83822_config_wol()
223 return -EINVAL; in dp83822_config_wol()
237 if (wol->wolopts & WAKE_MAGIC) in dp83822_config_wol()
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H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include <linux/pse-pd/pse.h>
44 #include "phylib-internal.h"
45 #include "phy-caps.h"
149 /* 10/100 half/full*/ in features_init()
157 /* 100 full, TP */ in features_init()
167 /* 10/100 half/full + 1000 half/full */ in features_init()
178 /* 10/100 hal in features_init()
2886 phy_set_sym_pause(struct phy_device * phydev,bool rx,bool tx,bool autoneg) phy_set_sym_pause() argument
2910 phy_set_asym_pause(struct phy_device * phydev,bool rx,bool tx) phy_set_asym_pause() argument
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H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
131 * The value is calculated as following: (1/1000000)/((2^-32)/4)
137 * The value is calculated as following: (1/1000000)/((2^-32)/8)
566 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
570 if (type && type->interrupt_level_mask) in kszphy_config_intr()
571 mask = type->interrupt_level_mask; in kszphy_config_intr()
583 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr()
646 return -EINVAL; in kszphy_setup_led()
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
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