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/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/altr,tse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Triple Speed Ethernet MAC driver (TSE)
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
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/linux/drivers/net/ethernet/altera/
H A Daltera_msgdma.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera TSE SGDMA and MSGDMA Linux driver
12 /* No initialization work to do for MSGDMA */
30 /* Reset Rx mSGDMA */ in msgdma_reset()
31 csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, in msgdma_reset()
33 csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr, in msgdma_reset()
38 if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status), in msgdma_reset()
41 udelay(1); in msgdma_reset()
45 netif_warn(priv, drv, priv->dev, in msgdma_reset()
46 "TSE Rx mSGDMA resetting bit never cleared!\n"); in msgdma_reset()
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H A Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera TSE SGDMA and MSGDMA Linux driver
9 /* mSGDMA extended descriptor format
29 /* mSGDMA descriptor control field bit definitions
42 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
70 /* mSGDMA extended descriptor stride definitions
75 /* mSGDMA dispatcher control and status register map
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
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H A Daltera_utils.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera TSE SGDMA and MSGDMA Linux driver
26 return (value & bit_mask) ? 1 : 0; in tse_bit_is_set()
32 return (value & bit_mask) ? 0 : 1; in tse_bit_is_clear()
H A Daltera_sgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera TSE SGDMA and MSGDMA Linux driver
23 * bit 1: length error
34 * bit 1: read_fixed
45 #define SGDMA_STATUS_LENGTH_ERR BIT(1)
53 #define SGDMA_CONTROL_RD_FIXED BIT(1)
63 * bit 1: eop
73 * bit 1: interrupt on eop
80 * bits 8-15: max descriptors to generate interrupt
84 * bit 19-26: clocks before polling again
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H A Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
58 #define MAC_CMDCFG_RX_ENA BIT(1)
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
186 /* 12-bit receive FIFO section-empty threshold */
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H A Daltera_tse_main.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
30 #include <linux/mdio/mdio-regmap.h>
35 #include <linux/pcs-lynx.h>
50 static int debug = -1;
52 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
69 #define POLL_PHY (-1)
79 * finished transmitting at least 1/4 of the packets in the queue.
81 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
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H A Daltera_sgdma.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera TSE SGDMA and MSGDMA Linux driver
56 priv->txctrlreg = SGDMA_CTRLREG_ILASTD | in sgdma_initialize()
59 priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP | in sgdma_initialize()
63 INIT_LIST_HEAD(&priv->txlisthd); in sgdma_initialize()
64 INIT_LIST_HEAD(&priv->rxlisthd); in sgdma_initialize()
66 priv->rxdescphys = (dma_addr_t) 0; in sgdma_initialize()
67 priv->txdescphys = (dma_addr_t) 0; in sgdma_initialize()
69 priv->rxdescphys = dma_map_single(priv->device, in sgdma_initialize()
70 (void __force *)priv->rx_dma_desc, in sgdma_initialize()
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/linux/Documentation/networking/device_drivers/ethernet/altera/
H A Daltera_tse.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Altera Triple-Speed Ethernet MAC driver
9 Copyright |copy| 2008-2014 Altera Corporation
11 This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers
12 using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
24 The Triple-Speed Ethernet, SGDMA, and MSGDMA components are all soft IP
31 Triple-Speed Ethernet instance is using an SGDMA or MSGDMA component. The
36 The SGDMA component is to be deprecated in the near future (over the next 1-2
37 years as of this writing in early 2014) in favor of the MSGDMA component.
43 therefore will not perform as well compared to the MSGDMA soft IP. Please
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/linux/arch/nios2/boot/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
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