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Searched +full:tsc +full:- +full:irq (Results 1 – 25 of 73) sorted by relevance

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/linux/drivers/input/touchscreen/
H A Dlpc32xx_ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPC32xx built-in touchscreen driver
43 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
57 #define MOD_NAME "ts-lpc32xx"
60 __raw_readl((dev)->tsc_base + (reg))
62 __raw_writel((val), (dev)->tsc_base + (reg))
67 int irq; member
71 static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc) in lpc32xx_fifo_clear() argument
73 while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) & in lpc32xx_fifo_clear()
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H A Dimx6ul_tsc.c1 // SPDX-License-Identifier: GPL-2.0
57 /* TSC registers */
68 /* TSC configuration registers field define */
100 * TSC module need ADC to get the measure value. So
101 * before config TSC, we should initialize ADC module.
103 static int imx6ul_adc_init(struct imx6ul_tsc *tsc) in imx6ul_adc_init() argument
111 reinit_completion(&tsc->completion); in imx6ul_adc_init()
113 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
118 if (tsc->average_enable) { in imx6ul_adc_init()
120 adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT; in imx6ul_adc_init()
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H A Dtsc2007_core.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * - ads7846.c
12 * - corgi_ts.c
13 * Copyright (C) 2004-2005 Richard Purdie
14 * - omap_ts.[hc], ads7846.h, ts_osk.c
31 int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd) in tsc2007_xfer() argument
36 data = i2c_smbus_read_word_data(tsc->client, cmd); in tsc2007_xfer()
38 dev_err(&tsc->client->dev, "i2c io error: %d\n", data); in tsc2007_xfer()
44 * Where DataLow has [D11-D4], DataHigh has [D3-D0 << 4 | Dummy 4bit]. in tsc2007_xfer()
48 dev_dbg(&tsc->client->dev, "data: 0x%x, val: 0x%x\n", data, val); in tsc2007_xfer()
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H A Dcy8ctmg110_ts.c1 // SPDX-License-Identifier: GPL-2.0-only
52 * is being powered off or on. When powering on this routine de-asserts
57 if (ts->reset_gpio) in cy8ctmg110_power()
58 gpiod_set_value_cansleep(ts->reset_gpio, !poweron); in cy8ctmg110_power()
61 static int cy8ctmg110_write_regs(struct cy8ctmg110 *tsc, unsigned char reg, in cy8ctmg110_write_regs() argument
64 struct i2c_client *client = tsc->client; in cy8ctmg110_write_regs()
75 dev_err(&client->dev, "i2c write data cmd failed\n"); in cy8ctmg110_write_regs()
76 return ret < 0 ? ret : -EIO; in cy8ctmg110_write_regs()
82 static int cy8ctmg110_read_regs(struct cy8ctmg110 *tsc, in cy8ctmg110_read_regs() argument
85 struct i2c_client *client = tsc->client; in cy8ctmg110_read_regs()
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H A Dti_am335x_tsc.c4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
35 #define MAX_12BIT ((1 << 12) - 1)
50 unsigned int irq; member
64 return readl(ts->mfd_tscadc->tscadc_base + reg); in titsc_readl()
67 static void titsc_writel(struct titsc *tsc, unsigned int reg, in titsc_writel() argument
70 writel(val, tsc->mfd_tscadc->tscadc_base + reg); in titsc_writel()
81 * Get the order in which TSC wires are attached in titsc_config_wires()
84 analog_line[i] = (ts_dev->config_inp[i] & 0xF0) >> 4; in titsc_config_wires()
85 wire_order[i] = ts_dev->config_inp[i] & 0x0F; in titsc_config_wires()
87 return -EINVAL; in titsc_config_wires()
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H A Dtsc2007.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * - ads7846.c
11 * - corgi_ts.c
12 * Copyright (C) 2004-2005 Richard Purdie
13 * - omap_ts.[hc], ads7846.h, ts_osk.c
44 #define MAX_12BIT ((1 << 12) - 1)
75 int irq; member
86 int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd);
87 u32 tsc2007_calculate_resistance(struct tsc2007 *tsc, struct ts_event *tc);
/linux/drivers/thermal/tegra/
H A Dtegra30-tsensor.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2021 GRATE-DRIVER project
95 err = reset_control_assert(ts->rst); in tegra_tsensor_hw_enable()
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
101 err = clk_prepare_enable(ts->clk); in tegra_tsensor_hw_enable()
103 dev_err(ts->dev, "failed to enable clock: %d\n", err); in tegra_tsensor_hw_enable()
109 err = reset_control_deassert(ts->rst); in tegra_tsensor_hw_enable()
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
128 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0); in tegra_tsensor_hw_enable()
129 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0); in tegra_tsensor_hw_enable()
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/linux/drivers/clocksource/
H A Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
89 struct clocksource tsc; member
95 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
100 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
105 return readl_relaxed(wdt->regs + offset); in wdt_readl()
114 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
116 return ERR_PTR(-ENOMEM); in tegra186_tmr_create()
118 tmr->parent = tegra; in tegra186_tmr_create()
119 tmr->regs = tegra->regs + offset; in tegra186_tmr_create()
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H A Dhyperv_timer.c1 // SPDX-License-Identifier: GPL-2.0
5 * provided by the Hyper-V hypervisor to guest VMs, as described
6 * in the Hyper-V Top Level Functional Spec (TLFS). This driver
22 #include <linux/irq.h>
36 * mechanism is used when running on older versions of Hyper-V
37 * that don't support Direct Mode. While Hyper-V provides
44 * However, for legacy versions of Hyper-V when Direct Mode
51 static int stimer0_irq = -1;
64 ce->event_handler(ce); in hv_stimer0_isr()
70 * per-cpu interrupts, which also implies Direct Mode.
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/linux/arch/x86/xen/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
30 #include "xen-ops.h"
37 /* Get the TSC speed from Xen */
41 &HYPERVISOR_shared_info->vcpu_info[0].time; in xen_tsc_khz()
53 src = &__this_cpu_read(xen_vcpu)->time; in xen_clocksource_read()
69 src = &__this_cpu_read(xen_vcpu)->time; in xen_sched_clock()
71 ret -= xen_sched_clock_offset; in xen_sched_clock()
79 struct pvclock_wall_clock *wall_clock = &(s->wc); in xen_read_wallclock()
82 vcpu_time = &get_cpu_var(xen_vcpu)->time; in xen_read_wallclock()
94 return -ENODEV; in xen_set_wallclock()
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/linux/drivers/mfd/
H A Dmax8925-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Marvell International Ltd.
12 #include <linux/irq.h>
28 .name = "max8925-backlight",
31 .id = -1,
37 .name = "max8925-tsc",
46 .name = "max8925-touch",
49 .id = -1,
55 .name = "max8925-power",
64 .name = "max8925-power",
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H A Dmax8925-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
55 mutex_lock(&chip->io_lock); in max8925_reg_read()
57 mutex_unlock(&chip->io_lock); in max8925_reg_read()
72 mutex_lock(&chip->io_lock); in max8925_reg_write()
74 mutex_unlock(&chip->io_lock); in max8925_reg_write()
86 mutex_lock(&chip->io_lock); in max8925_bulk_read()
88 mutex_unlock(&chip->io_lock); in max8925_bulk_read()
100 mutex_lock(&chip->io_lock); in max8925_bulk_write()
102 mutex_unlock(&chip->io_lock); in max8925_bulk_write()
115 mutex_lock(&chip->io_lock); in max8925_set_bits()
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H A Dti_am335x_tscadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
33 spin_lock_irqsave(&tscadc->reg_lock, flags); in am335x_tsc_se_set_cache()
34 tscadc->reg_se_cache |= val; in am335x_tsc_se_set_cache()
35 if (tscadc->adc_waiting) in am335x_tsc_se_set_cache()
36 wake_up(&tscadc->reg_se_wait); in am335x_tsc_se_set_cache()
37 else if (!tscadc->adc_in_use) in am335x_tsc_se_set_cache()
38 regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); in am335x_tsc_se_set_cache()
40 spin_unlock_irqrestore(&tscadc->reg_lock, flags); in am335x_tsc_se_set_cache()
49 regmap_read(tscadc->regmap, REG_ADCFSM, &reg); in am335x_tscadc_need_adc()
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
14 3) TSC Hardware
32 information relevant to KVM and hardware-based virtualization.
37 First we discuss the basic hardware devices available. TSC and the related
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
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/linux/arch/x86/kernel/cpu/
H A Dmshyperv.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/irq.h>
50 return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0; in hv_get_nested_msr()
143 * Routines to do per-architecture handling of stimer0
232 * Hyper-V clock counter resets during hibernation. Save and restore clock
234 * before suspend. This is to make sure that sched_clock using hv tsc page
246 * Adjust the offsets used by hv tsc clocksource to in restore_hv_clock_tsc_state()
249 * - reference counter (time) now. in restore_hv_clock_tsc_state()
251 hv_adj_sched_clock_offset(hv_ref_counter_at_suspend - hv_read_reference_counter()); in restore_hv_clock_tsc_state()
256 * functions of x86_platform. The Hyper-V clock counter is reset during
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/linux/Documentation/devicetree/bindings/mfd/
H A Dmaxim,max8925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lee Jones <lee@kernel.org>
22 interrupt-controller: true
24 "#interrupt-cells":
27 The cell is the IRQ number
29 maxim,tsc-irq:
37 "^SDV[1-3]$|^LDO[1-9]$|^LDO1[0-9]$|^LDO20$":
38 description: regulator configuration for SDV1-3 and LDO1-20
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/linux/Documentation/virt/kvm/devices/
H A Dvcpu.rst1 .. SPDX-License-Identifier: GPL-2.0
9 kvm_device_attr as other devices, but targets VCPU-wide settings and controls.
19 ------
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/linux/include/linux/mfd/
H A Dti_am335x_tscadc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
40 /* IRQ wakeup enable */
43 /* IRQ enable */
161 int irq; member
171 /* tsc device */
172 struct titsc *tsc; member
180 struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data; in ti_tscadc_dev_get()
187 return of_device_is_compatible(tscadc->dev->of_node, in ti_adc_with_touchscreen()
188 "ti,am3359-tscadc"); in ti_adc_with_touchscreen()
/linux/Documentation/driver-api/hte/
H A Dtegra-hte.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 -----------
10 (Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
11 from the system counter TSC which has 31.25MHz clock rate, and the driver
15 --------
31 specified during IOCTL calls. Refer to ``tools/gpio/gpio-event-mon.c``, which
34 LIC (Legacy Interrupt Controller) IRQ GTE
35 -----------------------------------------
37 This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
39 provides an example of how a consumer can request an IRQ line. Since it is a
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/linux/arch/x86/kernel/
H A Dhpet.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/irq.h>
30 unsigned int irq; member
134 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
201 * is wrong for i8259!) not the output IRQ. Many BIOS writers in hpet_reserve_platform_timers()
211 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
213 switch (hc->mode) { in hpet_reserve_platform_timers()
216 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
220 hpet_reserve_timer(&hd, hc->num); in hpet_reserve_platform_timers()
236 if (hc->mode == HPET_MODE_UNUSED) { in hpet_select_device_channel()
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H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/irq.h>
37 static irqreturn_t timer_interrupt(int irq, void *dev_id) in timer_interrupt() argument
39 global_clock_event->event_handler(global_clock_event); in timer_interrupt()
90 * Initialize TSC and delay the periodic timer init to
103 if (cs->vdso_clock_mode == VDSO_CLOCKMODE_NONE) in clocksource_arch_init()
106 if (cs->mask != CLOCKSOURCE_MASK(64)) { in clocksource_arch_init()
108 cs->name, cs->mask); in clocksource_arch_init()
109 cs->vdso_clock_mode = VDSO_CLOCKMODE_NONE; in clocksource_arch_init()
/linux/arch/x86/kvm/
H A Dx86.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
16 * Ben-Ami Yassour <benami@il.ibm.com>
21 #include "irq.h"
48 #include <linux/user-return-notifier.h>
62 #include <linux/entry-kvm.h>
109 ((struct kvm_vcpu *)(ctxt)->vcpu)
112 * - enable syscall per default because its emulated by KVM
113 * - enable LME and LMA per default on 64 bit KVM
144 *(((struct kvm_x86_ops *)0)->func));
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/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra186-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
24 The Tegra186 timer provides ten 29-bit timer counters.
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/linux/drivers/hte/
H A Dhte-tegra194.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 NVIDIA Corporation
23 /* HTE source clock TSC is 31.25MHz */
28 #define NV_AON_SLICE_INVALID -1
80 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN)
354 return readl(hte->regs + reg); in tegra_hte_readl()
360 writel(val, hte->regs + reg); in tegra_hte_writel()
370 return -EINVAL; in tegra_hte_map_to_line_id()
372 return -EINVAL; in tegra_hte_map_to_line_id()
393 return -EINVAL; in tegra_hte_line_xlate()
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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-buttress.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
11 #include <linux/dma-mapping.h>
26 #include "ipu6-bus.h"
27 #include "ipu6-dma.h"
28 #include "ipu6-buttress.h"
29 #include "ipu6-platform-buttress-regs.h"
67 struct ipu6_buttress *b = &isp->buttress; in ipu6_buttress_ipc_reset()
70 if (!isp->secure_mode) { in ipu6_buttress_ipc_reset()
71 dev_dbg(&isp->pdev->dev, "Skip IPC reset for non-secure mode"); in ipu6_buttress_ipc_reset()
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