tlb\-split (full) in projects: freebsd - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:tlb +full:- +full:split (Results 1 – 25 of 46) sorted by relevance

/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A D	fu540-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cell [all...]`
H A D	fu740-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c00 [all...]`
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A D	microchip-mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 6 #include "microchip-mpfs-fabric.dtsi" 9 #address-cells = <2>; 10 #size-cells = <2>; 15 #address-cells = <1>; 16 #size-cells = <0>; 21 i-cache-block-size = <64>; [all …]`
H A D	mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 21 i-cache-block-size = <64>; [all …]`
/freebsd/lib/libpmc/
H A D	pmc.haswell.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 325462-045US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 118 Bus lock and split lock requests. 128 M-state initial lookup stat in L3. [all …]`
H A D	pmc.haswellxeon.3	`46 .Bl -tag -width "Li PMC_CLASS_IAP" 48 Fixed-function counters that count only one hardware event per counter. 60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62 .%N "Order Number: 325462-052US" 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 90 Configure the Off-core Response bits. 91 .Bl -tag -width indent 119 Bus lock and split lock requests. 129 M-state initial lookup stat in L3. [all …]`
H A D	pmc.sandybridge.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 64 .%N "Order Number: 253669-039US" 73 .Bl -column "PMC_CAP_INTERRUPT" "Support" 90 .Bl -tag -width indent 92 Configure the Off-core Response bits. 93 .Bl -tag -width indent 120 Bus lock and split lock requests. 130 M-state initial lookup stat in L3. [all …]`
H A D	pmc.sandybridgexeon.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 253669-043US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 117 Bus lock and split lock requests. 127 M-state initial lookup stat in L3. [all …]`
H A D	pmc.ivybridgexeon.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60 .%N "Order Number: 325462-045US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 116 Bus lock and split lock requests. 126 M-state initial lookup stat in L3. [all …]`
H A D	pmc.ivybridge.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60 .%N "Order Number: 253669-043US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 116 Bus lock and split lock requests. 126 M-state initial lookup stat in L3. [all …]`
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A D	jh7100.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; 18 #size-cells = <0>; 21 compatible = "sifive,u74-mc", "riscv"; 23 d-cache-block-size = <64>; [all …]`
H A D	jh7110.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive,jh7110-crg.h> 9 #include <dt-bindings/power/starfive,jh7110-pmu.h> 10 #include <dt-bindings/reset/starfive,jh7110-crg.h> 11 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 19 #address-cells = <1>; 20 #size-cells = <0>; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A D	cpus.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V CPUs 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 This document uses some terminology common to the RISC-V community 19 mandated by the RISC-V ISA: a PC and some registers. This 27 - $ref: /schemas/cpu.yaml# [all …]`
/freebsd/crypto/openssl/util/
H A D	add-depends.pl	2 # Copyright 2018-2021 The OpenSSL Project Authors. All Rights Reserved. 42 ( ( grep { $unified_info{sources}->{$_}->[0] =~ /\.cc?$/ } 44 ( grep { $unified_info{shared_sources}->{$_}->[0] =~ /\.cc?$/ } 88 # Split the line into individual header files, and keep those 91 for (split(/\s+/, $line)) { 95 if (-f $x) { 103 print STDERR "DEBUG[$producer]: ignoring $objfile <- $line\n" 114 # well with out-of-source-tree builds, so we must resort to tricks 169 # extension .TLB. We also know that our header files aren't stored 172 # .TLB. [all …]
/freebsd/sys/amd64/include/
H A D	vmparam.h	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 77 * TLB pressure. 91 * largest physical address that is accessible by ISA DMA is split 100 * VM_FREEPOOL_LAZYINIT is a special-purpose pool that is populated only during 134 * page TLB misses and cache misses caused by 2MB page TLB misses. 157 * Kernel physical load address for non-UEFI boot and for legacy UEFI loader. 170 * 0x0000000000000000 - 0x00007fffffffffff user map 171 * 0x0000800000000000 - 0xffff7fffffffffff does not exist (hole) 172 * 0xffff800000000000 - 0xffff804020100fff recursive page table (512GB slot) [all …]
/freebsd/sys/riscv/include/
H A D	vmparam.h	1 /- 94 page TLB misses and cache misses caused by 4MB page TLB misses. 115 * RISC-V implements multiple paging modes with different virtual address space 117 * FreeBSD. SV39 provides a 512GB virtual address space and uses three-level 119 * four-level page tables. 64-bit RISC-V implementations are required to provide 123 * The address space is split into two regions at each end of the 64-bit address 129 * 0x0000000000000000 - 0x0000003fffffffff 256GB user map 130 * 0x0000004000000000 - 0xffffffbfffffffff unmappable 131 * 0xffffffc000000000 - 0xffffffc7ffffffff 32GB kernel map 132 * 0xffffffc800000000 - 0xffffffcfffffffff 32GB unused [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	33 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 … 108 …he core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO … 118 …cles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DR… 125 … an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-… 130 …ts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in t… 137 …re is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit i… 142 …ts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in t… 149 …re is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit i… 154 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 164 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", [all …]
/freebsd/sys/arm64/include/
H A D	vmparam.h	1 /- 79 VM_FREEPOOL_LAZYINIT is a special-purpose pool that is populated only during 98 * to optimize the use of the direct map by UMA. Specifically, a 64-byte 102 * both 2MB page TLB misses and cache misses during the page table walk when 103 * a 2MB page TLB miss does occur. 150 * split into 2 regions at each end of the 64 bit address space, with an 239 * - PHYS_IN_DMAP_RANGE will return true that may be within the DMAP range 242 * - PHYS_IN_DMAP will check if DMAP address is mapped before returning true. 262 ((pa) - dmap_phys_base) + DMAP_MIN_ADDRESS; \ 270 ((va) - DMAP_MIN_ADDRESS) + dmap_phys_base; \ [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/alderlake/
H A D	cache.json	3 …he core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO … 14 …cles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DR… 25 …ts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in t… 36 …ts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in t… 47 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 58 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 327 "BriefDescription": "Counts all the retired split loads.", 476 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MIS… 575 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.M… 706 "BriefDescription": "Retired load instructions that split across a cacheline boundary.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 94 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 100 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 177 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 188 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 237 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 243 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques… 284 "PublicDescription": "Counts all retired memory instructions - loads and stores.", 302 "BriefDescription": "Retired load instructions that split across a cacheline boundary.", [all …]
/freebsd/sys/arm64/iommu/
H A D	smmureg.h	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 40 #define IDR0_ST_LVL_2 (0x1 << IDR0_ST_LVL_S) /* 2-level Stream Table/ 52 #define IDR0_CD2L (1 << 19) / 2-level Context descriptor table/ 53 #define IDR0_VMID16 (1 << 18) / 16-bit VMID supported / 54 #define IDR0_VMW (1 << 17) / VMID wildcard-matching / 57 #define IDR0_SEV (1 << 14) / WFE wake-up events / 59 #define IDR0_ASID16 (1 << 12) / 16-bit ASID supported / 60 #define IDR0_NS1ATS (1 << 11) / Split-stage ATS not supported */ [all …]
/freebsd/sys/arm/include/
H A D	armreg.h	`3 /- 4 SPDX-License-Identifier: BSD-4-Clause 7 * Copyright (c) 1994-1996 Mark Brinicombe. 69 /* The high-order byte is always the implementor / 88 / On recent ARMs this byte holds the architecture and variant (sub-model) / 145 / XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 / 165 #define CPU_ID_MV88FR571_VD 0x56155710 / Marvell Feroceon 88FR571-V [all...]`
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A D	TreeTransform.h	1 //===------- TreeTransform.h - Semantic Tree Transformation ------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 66 /// transformation is performed for non-type template parameters and 69 /// This tree-transformation template uses static polymorphism to allow 75 /// Semantic tree transformations are split into two stages, either of which 86 /// most coarse-grained transformations involve replacing TransformType(), 91 /// For more fine-grained transformations, subclasses can replace any of the 106 /// default locations and entity names used for type-checking [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re… 161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi… 203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi… 215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch … 221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch … 371 "BriefDescription": "IFU Finished a (non-branch) instruction", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 65 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 103 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 109 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 125 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MIS… 131 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc… 235 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.M… 241 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc… 263 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 274 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", [all …]