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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-pisp-be.rst18 The PiSP Back End processes images in tiles, and its configuration requires
31 to be processed and is therefore shared across all the tiles of the image. So
33 across all tiles from the same frame.
41 As the ISP processes images in tiles, each set of tiles parameters describe how
43 parameters consist of 160 bytes of data and to process a batch of tiles several
44 sets of tiles parameters are required.
46 Tiles parameters are passed to the ISP by populating the member of
H A Dpixfmt-yuv-planar.rst103 - 64x32 tiles
112 - 16x16 tiles
126 - 4x4 tiles
154 - 4x4 tiles
161 - 16x32 / 16x16 tiles tiled low bits
168 - 16x32 / 16x16 tiles raster low bits
390 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
395 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
399 If the vertical resolution is an odd number of tiles, the last row of
400 tiles is stored in linear order. The layouts of the luma and chroma
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
H A Darm,vexpress-juno.yaml18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
131 description: When describing tiles consisting of more than one DCC, its
140 the connection between the motherboard and any tiles. Sometimes the
/linux/include/uapi/drm/
H A Ddrm_fourcc.h561 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
578 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
596 * This is a tiled layout using 4Kb tiles in row-major layout.
597 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
617 * considered to be made up of normal 128Bx32 Y tiles, Thus
632 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
643 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
666 * corresponds to an area of 4x1 tiles in the main surface. The main surface
674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
722 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h103 * must be configured in terms of the number of tiles in X & Y axis.
123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.
143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size
150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size
/linux/include/drm/intel/
H A Dxe_sriov_vfio.h35 * This function will wait until VF FLR is processed by PF on all tiles (or
47 * This function will pause VF on all tiles/GTs.
58 * This function will resume VF on all tiles.
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c275 struct vdec_vp9_slice_tiles tiles; member
887 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile() local
897 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile()
898 tiles->actual_rows = 0; in vdec_vp9_slice_setup_tile()
911 tiles->mi_rows[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
912 if (tiles->mi_rows[i]) in vdec_vp9_slice_setup_tile()
913 tiles->actual_rows++; in vdec_vp9_slice_setup_tile()
920 tiles->mi_cols[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
1058 * parse tiles according to `6.4 Decode tiles syntax`
1061 * frame contains uncompress header, compressed header and several tiles.
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/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
H A Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
H A Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
H A Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
H A Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
/linux/drivers/gpu/drm/xe/
H A Dxe_device_types.h149 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
187 * still be accessed by all tiles' GTs.
195 * still be accessed by all tiles' GTs.
299 /** @info.tile_count: Number of tiles */
522 /** @tiles: device tiles */
523 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; member
H A Dxe_tile_sysfs_types.h17 * When dealing with multiple TILEs, this struct helps to understand which
/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c27 * of 4*4 or 16 tiles. A conversion is then carried out for each
34 * of tiles as the output frame:
62 * output image. Tiles are numbered row major from top left to bottom
347 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", in dump_format()
389 * Calculate downsizing coefficients, which are the same for all tiles,
392 * Also determine the number of tiles necessary to guarantee that no tile
448 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", in calc_image_resize_coefficients()
526 * Output tiles must start at a multiple of 8 bytes horizontally and in find_best_seam()
538 * Tiles in the right row / bottom column may not be allowed to in find_best_seam()
647 * Fill in left position and width and for all tiles in an input column, and
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c63 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
979 unsigned int tiles; in intel_adjust_tile_offset() local
985 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
987 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
988 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
1090 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
1105 tiles = *x / tile_width; in intel_compute_aligned_offset()
1108 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
1418 * of 8 main surface tiles. in plane_view_dst_stride_tiles()
1611 /* Return number of tiles @color_plane needs. */
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/linux/drivers/video/fbdev/
H A Dgbefb.c689 The GBE hardware uses a tiled memory to screen mapping. Tiles are in gbefb_set_par()
692 tiles on the right and/or bottom of the screen if needed. in gbefb_set_par()
710 Tiles have the advantage that they can be allocated individually in in gbefb_set_par()
716 Tiles are still allocated as independent chunks of 64KB of in gbefb_set_par()
751 /* Tell gbe about the tiles table location */ in gbefb_set_par()
1159 printk(KERN_ERR "gbefb: couldn't allocate tiles table\n"); in gbefb_probe()
1193 /* map framebuffer memory into tiles table */ in gbefb_probe()
/linux/arch/arm/include/debug/
H A Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
/linux/drivers/gpu/drm/
H A Ddrm_client_modeset.c461 /* if this tile_pass doesn't cover any of the tiles - keep going */ in drm_client_target_preferred()
466 * all tiles left and above in drm_client_target_preferred()
490 * In case of tiled mode if all tiles not present fallback to in drm_client_target_preferred()
492 * After all tiles are present, try to find the tiled mode in drm_client_target_preferred()
495 * tile 0,0 and set to no mode for all other tiles. in drm_client_target_preferred()
746 * In case of tiled modes, if all tiles are not present in drm_client_firmware_config()
/linux/Documentation/devicetree/bindings/media/
H A Draspberrypi,pispbe.yaml16 in tiles and produces images consumable by applications.
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h364 /* Specifies the number of tiles in the x direction
371 /* Specifies the number of tiles in the y direction to
409 * THIN tiles use an 8x8x1 tile size.
410 * THICK tiles use an 8x8x4 tile size.
/linux/drivers/media/platform/verisilicon/
H A Dhantro_hevc.c90 /* Need to reallocate due to tiles passed via PPS */ in tile_buffer_reallocate()
260 * Maximum number of tiles times width and height (2 bytes each), in hantro_hevc_dec_init()

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