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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-pisp-be.rst17 The PiSP Back End processes images in tiles, and its configuration requires
30 to be processed and is therefore shared across all the tiles of the image. So
32 across all tiles from the same frame.
40 As the ISP processes images in tiles, each set of tiles parameters describe how
42 parameters consist of 160 bytes of data and to process a batch of tiles several
43 sets of tiles parameters are required.
45 Tiles parameters are passed to the ISP by populating the member of
H A Dpixfmt-yuv-planar.rst102 - 64x32 tiles
111 - 16x16 tiles
125 - 4x4 tiles
146 - 4x4 tiles
153 - 16x32 / 16x16 tiles tiled low bits
160 - 16x32 / 16x16 tiles raster low bits
324 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
329 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
333 If the vertical resolution is an odd number of tiles, the last row of
334 tiles is stored in linear order. The layouts of the luma and chroma
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
H A Darm,vexpress-juno.yaml18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
130 description: When describing tiles consisting of more than one DCC, its
139 the connection between the motherboard and any tiles. Sometimes the
/linux/Documentation/accel/amdxdna/
H A Damdnpu.rst29 AMD XDNA Array comprises of 2D array of compute and memory tiles built with
30 `AMD AI Engine Technology`_. Each column has 4 rows of compute tiles and 1
40 compute tiles arranged into 5 columns. AMD Strix Point client APU have 4x8
41 topology, i.e., 4 rows of compute tiles arranged into 8 columns.
46 The single row of memory tiles create a pool of software managed on chip L2
47 memory. DMA engines are used to move data between host DDR and memory tiles.
153 configuration and ELF for the compute tiles. The overlay is loaded on the
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h103 * must be configured in terms of the number of tiles in X & Y axis.
123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.
143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size
150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size
/linux/include/uapi/drm/
H A Ddrm_fourcc.h505 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
522 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
540 * This is a tiled layout using 4Kb tiles in row-major layout.
541 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
561 * considered to be made up of normal 128Bx32 Y tiles, Thus
576 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
587 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
610 * corresponds to an area of 4x1 tiles in the main surface. The main surface
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
666 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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H A Damdxdna_accel.h67 * @num_tiles: Number of AIE tiles.
285 * @core: The metadata for all core tiles.
286 * @mem: The metadata for all mem tiles.
287 * @shim: The metadata for all shim tiles.
/linux/drivers/gpu/drm/xe/
H A Dxe_device.h60 return &xe->tiles[0]; in xe_device_get_root_tile()
91 gt = xe->tiles[gt_id].primary_gt; in xe_device_get_gt()
127 for_each_if((tile__) = &(xe__)->tiles[(id__)])
131 for_each_if((tile__) = &(xe__)->tiles[(id__)])
H A Dxe_device_types.h157 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
202 * still be accessed by all tiles' GTs.
288 /** @info.tile_count: Number of tiles */
431 /** @tiles: device tiles */
432 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; member
H A Dxe_tile.c31 * tiles together in a way such that interrupt notifications from remote tiles
H A Dxe_tile_sysfs_types.h17 * When dealing with multiple TILEs, this struct helps to understand which
/linux/drivers/video/fbdev/core/
H A DKconfig204 where the screen is divided into rectangular sections (tiles), whereas
207 parameters in terms of number of tiles instead of number of pixels.
211 terms of number of tiles in the x- and y-axis.
/linux/include/linux/
H A Dfb.h330 __u32 length; /* number of tiles in the map */
338 __u32 width; /* number of tiles in the x-axis */
339 __u32 height; /* number of tiles in the y-axis */
351 __u32 width; /* number of tiles in the x-axis */
352 __u32 height; /* number of tiles in the y-axis */
358 __u32 width; /* number of tiles in the x-axis */
359 __u32 height; /* number of tiles in the y-axis */
362 __u32 length; /* number of tiles to draw */
379 /* all dimensions from hereon are in terms of tiles */
381 /* move a rectangular region of tiles from one area to another*/
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/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
H A Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
H A Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
H A Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
H A Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c275 struct vdec_vp9_slice_tiles tiles; member
887 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile() local
897 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile()
898 tiles->actual_rows = 0; in vdec_vp9_slice_setup_tile()
911 tiles->mi_rows[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
912 if (tiles->mi_rows[i]) in vdec_vp9_slice_setup_tile()
913 tiles->actual_rows++; in vdec_vp9_slice_setup_tile()
920 tiles->mi_cols[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
1058 * parse tiles according to `6.4 Decode tiles syntax`
1061 * frame contains uncompress header, compressed header and several tiles.
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/linux/drivers/gpu/drm/xe/display/
H A Dxe_fb_pin.c41 /* The DE ignores the PTEs for the padding tiles */ in write_dpt_rotated()
72 /* The DE ignores the PTEs for the padding tiles */ in write_dpt_remapped()
98 /* display uses 4K tiles instead of bytes here, convert to entries.. */ in __xe_pin_fb_vma_dpt()
187 /* The DE ignores the PTEs for the padding tiles */ in write_ggtt_rotated()
243 /* display seems to use tiles instead of bytes here, so convert it back.. */ in __xe_pin_fb_vma_ggtt()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c60 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
971 unsigned int tiles; in intel_adjust_tile_offset() local
977 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
979 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
980 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
1082 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
1097 tiles = *x / tile_width; in intel_compute_aligned_offset()
1100 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
1400 * of 8 main surface tiles. in plane_view_dst_stride_tiles()
1593 /* Return number of tiles @color_plane needs. */
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/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c27 * of 4*4 or 16 tiles. A conversion is then carried out for each
34 * of tiles as the output frame:
62 * output image. Tiles are numbered row major from top left to bottom
347 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", in dump_format()
403 * Calculate downsizing coefficients, which are the same for all tiles,
406 * Also determine the number of tiles necessary to guarantee that no tile
462 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", in calc_image_resize_coefficients()
540 * Output tiles must start at a multiple of 8 bytes horizontally and in find_best_seam()
552 * Tiles in the right row / bottom column may not be allowed to in find_best_seam()
661 * Fill in left position and width and for all tiles in an input column, and
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