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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 …rontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction … 12 …rontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction … 15 … frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction … 18 … frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction … 21 …d, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode er… 24 …d, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode er… 27 …backend interlock.This event counts every cycle that issue is stalled and there is an interlock. S… 30 …backend interlock.This event counts every cycle that issue is stalled and there is an interlock. S… 33 …d, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock th… 36 …d, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock th… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 … cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction … 24 … cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction … 27 …This event counts every cycle that the DPU instruction queue is empty and there is an instruction … 30 …This event counts every cycle that the DPU instruction queue is empty and there is an instruction … 39 …s event counts every cycle where the issue of an operation is stalled and there is an interlock. S… 42 …s event counts every cycle where the issue of an operation is stalled and there is an interlock. S… 45 …s event counts every cycle where the issue of an operation is stalled and there is an interlock on… 48 …s event counts every cycle where the issue of an operation is stalled and there is an interlock on… 51 … or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an i… 54 … or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an i… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A D	pipeline.json	15 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being proce… 20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p… 25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" 30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc… 35 …"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to… 40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." 45 "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" 50 "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
/linux/Documentation/locking/
H A D	robust-futexes.rst	18 that says "there's a waiter pending", and the sys_futex(FUTEX_WAIT) 23 value) that there were waiter(s) pending, and does the 26 state, and there's no in-kernel state associated with it. The kernel 27 completely forgets that there ever was a futex at that address. This 42 There is a big conceptual problem with futex based mutexes though: it is 44 the kernel cannot help with the cleanup: if there is no 'futex queue' 45 (and in most cases there is none, futexes being fast lightweight locks) 75 because the kernel has no knowledge about how many robust futexes there 89 At the heart of this new approach there is a per-thread private list of 93 time, the kernel checks this user-space list: are there any robust futex [all …]
/linux/Documentation/timers/
H A D	no_hz.rst	12 There are three main ways of managing scheduling-clock interrupts 38 there are some situations where this old-school approach is still the 40 that use short bursts of CPU, where there are very frequent idle 43 clock interrupts will normally be delivered any way because there 68 If a CPU is idle, there is little point in sending it a scheduling-clock 84 unnecessary scheduling-clock interrupts. In these situations, there 98 There is also a boot parameter "nohz=" that can be used to disable 107 If a CPU has only one runnable task, there is little point in sending it 108 a scheduling-clock interrupt because there is no other task to switch to. 121 by one less than the number of CPUs. In these situations, there is [all …]
/linux/Documentation/livepatch/
H A D	livepatch.rst	15 There are many situations where users are reluctant to reboot a system. It may 26 There are multiple mechanisms in the Linux kernel that are directly related 46 a live patch is called with the help of a custom ftrace handler. But there are 53 Functions are there for a reason. They take some input parameters, acquire or 64 But there are more complex fixes. For example, a patch might change 80 switching combined with kpatch's stack trace switching. There are also 119 (Note there's not yet such an approach for kthreads.) 142 There's also a /proc/<pid>/patch_state file which can be used to 150 actually delivered (there is no data in signal pending structures). Tasks are 155 /sys/kernel/livepatch/<patch>/force attribute. Writing 1 there clears [all …]
/linux/Documentation/process/
H A D	6.Followthrough.rst	13 It is a rare patch which is so good at its first posting that there is no 40 people remember who wrote kernel code, but there is little lasting fame 101 but there are times when somebody simply has to make a decision. If you 118 things. In particular, there may be more than one tree - one, perhaps, 122 For patches applying to areas for which there is no obvious subsystem tree 131 there's a good chance that you will get more comments from a new set of 151 To begin with, the visibility of your patch has increased yet again. There 153 the patch before. It may be tempting to ignore them, since there is no 162 where there are testers, there will be bug reports. 173 After any regressions have been dealt with, there may be other, ordinary [all …]
H A D	3.Early-stage.rst	44 There are a number of very good Linux kernel developers, but they 87 - There may be elements of the proposed solution which will not be 131 the MAINTAINERS file for a relevant place to post. If there is a suitable 132 subsystem list, posting there is often preferable to posting on 138 and not all subsystems are represented there. The person listed in the 140 that role currently. So, when there is doubt about who to contact, a 158 list of people to Cc for your patches. There are a number of options 178 matter is (1) kernel developers tend to be busy, (2) there is no shortage 186 not assume that it means there is no interest in the project. 187 Unfortunately, you also cannot assume that there are no problems with your [all …]
H A D	1.Intro.rst	11 encounter there. There are a great many reasons why kernel code should be 19 the patch development, review, and merging cycle are covered. There is some 29 patches are covered, and there is an introduction to some of the tools 91 intimidating to new developers, but there are good reasons and solid 99 frustrating experience. There is a lot of material here, but the effort 134 enable it. There is no need for driver disks, downloads, or the hassles 189 There are, however, additional factors which should be taken into account 201 is there regardless. 247 the licensing of the kernel is doomed to almost certain failure. There are 250 there is no prospect of a migration to version 3 of the GPL in the [all …]
/linux/arch/mips/vdso/
H A D	vgettimeofday.c	`24 * This is behind the ifdef so that we don't provide the symbol when there's no 25 * possibility of there being a usable clocksource, because there's nothing we 60 * This is behind the ifdef so that we don't provide the symbol when there's no 61 * possibility of there being a usable clocksource, because there's nothing we`
/linux/Documentation/networking/device_drivers/ethernet/toshiba/
H A D	spider_net.rst	28 There are three primary states that a descriptor can be in: "empty", 46 marks it full, and advances the GDACTDPA by one. Thus, when there is 55 and advance the tail pointer. Thus, when there is flowing RX traffic, 67 then mark the descr as "empty", ready to receive data. Thus, when there 117 the hardware can fill them, there is no problem. If, for some reason, 136 and is filling the next descrs. Since the OS doesn't see this, there 157 marked xa... which is "empty". Thus, from the OS point of view, there 158 is nothing to be done. In particular, there is the implicit assumption 168 and there can be no forward progress; the OS thinks there's nothing 177 operations there. Since this will leave "holes" in the ring, there [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	tlb.json	`4 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 8 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 36 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 40 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts …`
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	tlb.json	4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." 8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." 36 "PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an Address Translation (AT) instruction." 40 "PublicDescription": "Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count with an access from an Address Translation (AT) instruction."
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	tlb.json	`4 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 8 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 36 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts … 40 …there are multiple misses in the TLB that are resolved by the refill, then this event only counts …`
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	uncore-power.json	16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 52 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 61 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 70 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 79 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 88 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 97 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	uncore-power.json	16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 52 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 61 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 70 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 79 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 88 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 97 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
/linux/Documentation/filesystems/
H A D	debugfs.rst	14 there. The debugfs filesystem is also intended to not serve as a stable 15 ABI to user space; in theory, there are no stability constraints placed on 16 files exported there. The real world is not always so simple, though [1]_; 103 architectures, though, complicating the situation somewhat. There are 112 Similarly, there are helpers for variables of type unsigned long, in decimal 153 can be used to export binary information, but there does not appear to be 200 There is a helper function to create a device-related seq_file:: 212 There are a couple of other directory-oriented helper functions:: 226 There is one important thing that all debugfs users must take into account: 227 there i [all...]
H A D	ext2.rst	11 filesystem in use by Linux. There are also implementations available 79 separate patches). There is also a versioning mechanism to allow new 131 If the filesystem is revision 1 or higher, then there are extra fields, 151 There are some reserved fields which are currently unused in the inode 162 There are pointers to the first 12 blocks which contain the file's data 163 in the inode. There is a pointer to an indirect block (which contains 171 behaviour on a per-file basis. There are flags for secure deletion, 214 In ext2, there is a mechanism for reserving a certain number of blocks 240 revision 1. There are three 32-bit fields, one for compatible features 297 If you're exceptionally paranoid, there are 3 ways of making metadata [all …]
/linux/Documentation/arch/powerpc/
H A D	pci_iov_resource_on_powernv.rst	28 There is thus, in HW, a table of PE states that contains a pair of "frozen" 33 return all 1's value. MSIs are also blocked. There's a bit more state that 66 bridge being triggered. There's a PE# in the interrupt controller 75 from the CPU address space to the PCI address space. There is one M32 92 need to ensure Linux doesn't assign anything there, the M32 logic 115 address on the PowerBus). There is a way to also set the top 14 120 has 256 segments; however, there is no table for mapping a segment 124 there's a defined ordering for which window applies. 145 than one segment, we end up with more than one PE#. There is a HW 186 There are several strategies for isolating VFs in PEs: [all …]
/linux/Documentation/userspace-api/media/rc/
H A D	rc-protos.rst	32 This IR protocol uses manchester encoding to encode 14 bits. There is a 77 There is a variant of rc5 called either rc5x or extended rc5 78 where there the second stop bit is the 6th command bit, but inverted. 81 done to keep it compatible with plain rc-5 where there are two start bits. 191 The sony protocol is a pulse-width encoding. There are three variants, 218 The sony protocol is a pulse-width encoding. There are three variants, 245 The sony protocol is a pulse-width encoding. There are three variants, 356 The scancode is the exact 16 bits as in the protocol. There is also a 365 as in the protocol. There is also a toggle bit. 373 as in the protocol. There is also a toggle bit. [all …]
/linux/Documentation/power/
H A D	basic-pm-debugging.rst	49 there is the file /sys/power/pm_test that can be used to make the hibernation 50 core run in a test mode. There are 5 test modes available: 109 If the "freezer" test fails, there is a task that cannot be frozen (in that case 112 that there is a problem with the tasks freezer subsystem that should be 115 If the "devices" test fails, most likely there is a driver that cannot suspend 126 Once you have found the failing driver (there can be more than just one of 136 If the "platform" test fails, there is a problem with the handling of the 162 "reboot", "shutdown" and "platform" modes. If that does not work, there 165 individually. Otherwise, there is a problem with a modular driver and you can 168 - if there are n modules loaded and the attempt to suspend and resume fails, [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	uncore-power.json	16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 52 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 61 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 70 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 79 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 88 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 97 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
/linux/Documentation/core-api/
H A D	workqueue.rst	13 There are many cases where an asynchronous process execution context 22 While there are work items on the workqueue the worker executes the 24 there is no work item left on the workqueue the worker becomes idle. 91 There are two worker-pools, one for normal work items and the other 96 BH workqueues use the same framework. However, as there can only be one 97 concurrent execution context, there's no need to worry about concurrency. 129 stalling should be optimal. As long as there are one or more runnable 132 schedules a new worker so that the CPU doesn't sit idle while there 144 regulating concurrency level is on the users. There is also a flag to 164 also used as the name of the rescuer thread if there is one. [all …]
H A D	cachetlb.rst	47 there will be no entries in the TLB for 'mm'. 61 running, there will be no entries in the TLB for 'mm' for 86 is, after running, there will be no entries in the TLB for 144 the caches. That is, after running, there will be no cache 153 the caches. That is, after running, there will be no cache 166 addresses from the cache. After running, there will be no 194 After running, there will be no entries in the cache for 206 After running, there will be no entries in the cache for 217 there will be no entries in the cache for the kernel address 224 There exists another whole class of cpu cache issues which currently [all …]
/linux/Documentation/hid/
H A D	uhid.rst	7 relies heavily on the definitions declared there. 13 There is an example user-space application in ./samples/uhid/uhid-example.c 44 The "type" field defines the payload. For each type, there is a 55 followed by a UHID_OPEN event again and so on. There is no need to perform 96 This destroys the internal HID device. No further I/O will be accepted. There 99 You can create a new device by sending UHID_CREATE2 again. There is no need to 158 there is actually no other process that reads your data so there is no need to 162 This is sent when there are no more processes which read the HID data. It is 175 The kernel serializes GET_REPORT requests so there will never be two in

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