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Searched +full:th1520 +full:- +full:pwm (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/pwm/
H A Dpwm_th1520.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Rust T-HEAD TH1520 PWM driver
8 //! - The period and duty cycle are controlled by 32-bit hardware registers,
10 //! - The driver supports continuous output mode only; one-shot mode is not
12 //! - The controller hardware provides up to 6 PWM channels.
13 //! - Reconfiguration is glitch free - new period and duty cycle values are
15 //! - Polarity is handled via a simple hardware inversion bit; arbitrary
17 //! - Disabling a channel is achieved by configuring its duty cycle to zero to
32 pwm, time,
38 const fn th1520_pwm_chn_base(n: u32) -> usize { in th1520_pwm_chn_base()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
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/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
13 compatible = "thead,th1520";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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H A Dth1520-lichee-pi-4a.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "th1520-lichee-module-4a.dtsi"
10 compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
29 stdout-path = "serial0:115200n8";
32 thermal-zones {
33 cpu-thermal {
34 polling-delay = <1000>;
35 polling-delay-passive = <1000>;
36 thermal-sensors = <&pvt 0>;
39 fan_config0: fan-trip0 {
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dthead,th1520-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
15 The TH1520 has 3 groups of pads each controlled from different memory ranges.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
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/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
115 [TH1520_MUX_PWM] = "pwm",
284 TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
285 TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
286 TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
287 TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
80 will be called pinctrl-apple-gpio.
83 bool "Axis ARTPEC-6 pin controller driver"
88 This is the driver for the Axis ARTPEC-6 pin controller. This driver
91 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
100 functionality. This driver supports the pinmux, push-pull and
129 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
153 The Awinic AW9523/AW9523B is a multi-function I2C GPIO
154 expander with PWM functionality. This driver bundles a
180 called pinctrl-cy8c95x0.
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/linux/drivers/clk/thead/
H A Dclk-th1520-ap.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
10 #include <linux/clk-provider.h>
84 .mask = GENMASK(_width - 1, 0), \
132 regmap_read(common->map, common->cfg0, &val); in ccu_get_parent_helper()
133 parent = val >> mux->shift; in ccu_get_parent_helper()
134 parent &= GENMASK(mux->width - 1, 0); in ccu_get_parent_helper()
143 return regmap_update_bits(common->map, common->cfg0, in ccu_set_parent_helper()
144 GENMASK(mux->width - 1, 0) << mux->shift, in ccu_set_parent_helper()
145 index << mux->shift); in ccu_set_parent_helper()
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