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/linux/sound/soc/intel/common/
H A Dsoc-acpi-intel-tgl-match.c3 * soc-acpi-intel-tgl-match.c - tables and support for TGL ACPI enumeration.
512 .sof_tplg_filename = "sof-tgl-es8336", /* the tplg suffix is added at run time */
523 .sof_tplg_filename = "sof-tgl", /* the tplg suffix is added at run time */
533 .sof_tplg_filename = "sof-tgl-rt1308-ssp2-hdmi-ssp15.tplg"
734 .sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg",
740 .sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg",
746 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
752 .sof_tplg_filename = "sof-tgl-rt712.tplg",
758 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
764 .sof_tplg_filename = "sof-tgl-cs42l43-l3-cs35l56-l01.tplg",
[all …]
H A DMakefile8 soc-acpi-intel-tgl-match.o soc-acpi-intel-ehl-match.o \
/linux/arch/powerpc/platforms/powernv/
H A Dpci-ioda-tce.c375 struct iommu_table_group_link *tgl; in pnv_pci_unlink_table_and_group() local
384 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { in pnv_pci_unlink_table_and_group()
385 if (tgl->table_group == table_group) { in pnv_pci_unlink_table_and_group()
386 list_del_rcu(&tgl->next); in pnv_pci_unlink_table_and_group()
387 kfree_rcu(tgl, rcu); in pnv_pci_unlink_table_and_group()
414 struct iommu_table_group_link *tgl = NULL; in pnv_pci_link_table_and_group() local
419 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, in pnv_pci_link_table_and_group()
421 if (!tgl) in pnv_pci_link_table_and_group()
424 tgl->table_group = table_group; in pnv_pci_link_table_and_group()
425 list_add_rcu(&tgl->next, &tbl->it_group_list); in pnv_pci_link_table_and_group()
/linux/drivers/media/rc/img-ir/
H A Dimg-ir-rc5.c14 unsigned int addr, cmd, tgl, start; in img_ir_rc5_scancode() local
20 tgl = (raw >> 11) & 0x01; in img_ir_rc5_scancode()
34 request->toggle = tgl; in img_ir_rc5_scancode()
/linux/drivers/gpu/drm/i915/display/
H A Dskl_universal_plane_regs.h81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
91 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
257 #define PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE REG_BIT(15) /* TGL+ */
468 #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
512 /* tgl+ */
528 /* tgl+ */
543 /* tgl+ */
558 /* tgl+ */
H A Dintel_display_limits.h105 /* tgl+ */
H A Dintel_psr_regs.h62 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
H A Dintel_dmc.c165 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12)
594 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank in fixup_dmc_evt()
622 /* also disable the flip queue event on the main DMC on TGL */ in disable_dmc_evt()
627 /* also disable the HRR event on the main DMC on TGL/ADLS */ in disable_dmc_evt()
714 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ in need_pipedmc_load_program()
769 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. in can_enable_pipedmc()
H A Dintel_vrr.c101 * On ICL/TGL VRR hardware inserts one extra scanline in intel_vrr_extra_vblank_delay()
112 * ICL/TGL hardware imposes flipline>=vmin+1 in intel_vrr_vmin_flipline_offset()
266 * On TGL vmin/vmax/flipline also need to be in intel_vrr_hw_value()
614 * TGL: generate VRR "safe window" for DSB vblank waits in intel_vrr_set_transcoder_timings()
H A Dintel_cursor_regs.h107 /* tgl+ */
H A Dintel_color_regs.h82 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
H A Dintel_dp_mst.c89 * On TGL+, all the transcoders streaming on the same DDI port will indicate a
894 * On TGL+ this is required since each stream go through a master transcoder,
1077 * From TGL spec: "If multi-stream slave transcoder: Configure in mst_stream_post_disable()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c719 * Wa_1409142259:tgl,dg1,adl-p,adl-n in gen12_ctx_workarounds_init()
720 * Wa_1409347922:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
721 * Wa_1409252684:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
722 * Wa_1409217633:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
723 * Wa_1409207793:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
724 * Wa_1409178076:tgl,dg1,adl-p,adl-n in gen12_ctx_workarounds_init()
725 * Wa_1408979724:tgl,dg1,adl-p,adl-n in gen12_ctx_workarounds_init()
726 * Wa_14010443199:tgl,rkl,dg1,adl-p,adl-n in gen12_ctx_workarounds_init()
727 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p,adl-n in gen12_ctx_workarounds_init()
728 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p,adl-n in gen12_ctx_workarounds_init()
[all …]
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-dev.h17 #define TGL 0x0C macro
23 #define dcss_toggle(v, c) writel((v), (c) + TGL)
/linux/sound/soc/sof/intel/
H A Dtgl.c165 .platform = "tgl",
195 .platform = "tgl",
/linux/sound/soc/intel/avs/
H A DMakefile7 snd-soc-avs-y += skl.o apl.o cnl.o icl.o tgl.o mtl.o lnl.o ptl.o
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-mcd-phy.c33 * only 2 phys for TGL U and Y
38 * There are 2 MCD DPHY instances on TGL and 1 MCD DPHY instance on ADL.
110 /* for TGL-U, use 0x80000000 */
H A Dipu6.h35 * IPU6 - TGL
/linux/drivers/gpu/drm/i915/
H A Dintel_device_info.h112 /* TGL */
H A Di915_gem.c464 /* PREAD is disallowed for all platforms after TGL-LP. This also in i915_gem_pread_ioctl()
746 /* PWRITE is disallowed for all platforms after TGL-LP. This also in i915_gem_pwrite_ioctl()
/linux/sound/soc/intel/boards/
H A Dsof_ssp_amp.c52 /* BE ID defined in sof-tgl-rt1308-hdmi-ssp.m4 */
/linux/sound/soc/sof/
H A Dsof-pci-dev.c69 .driver_data = "sof-tgl-rt5682-ssp0-max98373-ssp2.tplg",
/linux/sound/hda/codecs/cirrus/
H A Dcs8409-tables.c600 SND_PCI_QUIRK(0x1028, 0x0BB5, "Warlock N3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
601 SND_PCI_QUIRK(0x1028, 0x0BB6, "Warlock V3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
/linux/drivers/usb/dwc3/
H A Ddwc3-pci.c442 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
/linux/sound/hda/core/
H A Dintel-dsp-config.c378 .ident = "UPX-TGL",

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