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/linux/drivers/gpu/drm/radeon/
H A Dradeon_drv.h73 * Add texture rectangle support for r100.
85 * 1.15- Add support for texture micro tiling
88 * texture filtering on r200
97 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
H A Dr600_cs.c1460 * @texture: texture's bo structure
1467 * the texture and mipmap bo object are big enough to cover this resource.
1470 struct radeon_bo *texture, in r600_check_texture_resource() argument
1546 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); in r600_check_texture_resource()
1550 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in r600_check_texture_resource()
1581 dev_warn(p->dev, "texture blevel %d > llevel %d\n", in r600_check_texture_resource()
1593 /* using get ib will give us the offset into the texture bo */ in r600_check_texture_resource()
1594 if ((l0_size + word2) > radeon_bo_size(texture)) { in r600_check_texture_resource()
1595 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1598 l0_size, radeon_bo_size(texture)); in r600_check_texture_resource()
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H A Dr300_reg.h232 * mode, the swizzling pattern is e.g. used to set zw components in texture
626 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
641 /* Only used for texture coordinates.
642 * Use the source field to route texture coordinate input from the
791 /* BEGIN: Texture specification */
794 * The texture specification dwords are grouped by meaning and not by texture
795 * unit. This means that e.g. the offset for texture image unit N is found in
965 /* END: Texture specification */
970 * There are separate instruction streams for texture instructions and ALU
1029 * As far as I can tell, texture instructions cannot write into output
H A Devergreen_cs.c755 struct radeon_bo *texture, in evergreen_cs_track_validate_texture() argument
794 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
815 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
820 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
829 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
831 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
837 /* check texture size */ in evergreen_cs_track_validate_texture()
839 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
853 if (toffset > radeon_bo_size(texture)) { in evergreen_cs_track_validate_texture()
854 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
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H A Dr300.c965 DRM_ERROR("Invalid texture format %u\n", in r300_packet0_check()
977 DRM_ERROR("Invalid texture format %u\n", in r300_packet0_check()
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,imr.yaml15 capture data or data in an external memory as 2D texture data and performing
16 texture mapping and drawing with respect to any shape that is split into
/linux/drivers/gpu/drm/vc4/
H A Dvc4_validate.c177 * never have a render target larger than 4096. The texture in vc4_check_tex_size()
675 DRM_DEBUG("Texture format %d unsupported\n", type); in reloc_tex()
695 /* The mipmap levels are stored before the base of the texture. Make in reloc_tex()
748 DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0); in reloc_tex()
749 DRM_INFO("Texture p1 at %d: 0x%08x\n", sample->p_offset[1], p1); in reloc_tex()
750 DRM_INFO("Texture p2 at %d: 0x%08x\n", sample->p_offset[2], p2); in reloc_tex()
751 DRM_INFO("Texture p3 at %d: 0x%08x\n", sample->p_offset[3], p3); in reloc_tex()
H A Dvc4_drv.h850 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
853 * This will be used at draw time to relocate the reference to the texture
860 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
861 * Setup") for definitions of the texture parameters.
875 * and validate the shader state record's uniforms that define the texture
/linux/drivers/char/agp/
H A DKconfig14 If you need more texture memory than you can get with the AGP GART
17 and have up to a couple gigs of texture space.
/linux/include/uapi/drm/
H A Dvc4_drm.h112 /* Pointer to uniform data and texture handles for the textures
117 * uniform data has a __u32 index into bo_handles per texture
119 * the program. Following the texture BO handle indices is the actual
H A Dradeon_drm.h406 /* Setup registers for each texture unit
680 int width; /* Texture image coordinates */
/linux/drivers/gpu/drm/v3d/
H A Dv3d_perfmon.c37 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
127 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
130 {"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"},
H A Dv3d_drv.c11 * pipelines), the TFU (texture formatting unit), and the CSD (compute
/linux/drivers/gpu/drm/vmwgfx/
H A Dvmw_surface_cache.h333 * @num_layers: Number of slices in an array texture or number of faces in
334 * a cubemap texture.
H A Dvmwgfx_binding.h84 * struct vmw_ctx_bindinfo_tex - texture stage binding metadata
H A Dvmwgfx_drv.h221 * @array_size: Number of array elements for a 1D/2D texture. For cubemap
222 texture number of faces * array_size. This should be 0 for pre
/linux/drivers/gpu/drm/i915/
H A Di915_scheduler_types.h41 * (e.g. we have to wait until the pixels have been rendering into a texture
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos850-clock.yaml269 - description: Image Texture Processing core clock (from CMU_TOP)
/linux/Documentation/fb/
H A Dsisfb.rst22 used by DRM/DRI for 3D texture and other data. This memory management is
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv50.c94 { 0x0000000a, "TEXTURE" },
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.c350 for (i = 0; i < 16; i++) { /* fragment texture units */ in nv40_gr_construct_state3d()
358 for (i = 0; i < 4; i++) { /* vertex texture units */ in nv40_gr_construct_state3d()
H A Dnv50.c347 case 6: /* texture error... unknown for now */ in nv50_gr_tp_trap()
585 /* TEXTURE: CUDA texturing units */ in nv50_gr_trap_handler()
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml2213 1 c0838000 c0834000 programmed in texture state
2574 texture using varying value directly before shader thread starts? I
2774 texture uploads, where a4xx blob would use normal draws. Used
2847 <doc>Texture sampler dwords</doc>
2891 different border-color states per texture.. Looks something like:
2907 <doc>Texture constant dwords</doc>
2945 …behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.bu…
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.h231 /* Whether texture coordinate truncation is conformant. */
/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_reg.h567 /* texture engine registers */

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