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Searched +full:tegra210 +full:- +full:emc +full:- +full:table (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra210-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
26 - description: external memory clock
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/freebsd/sys/contrib/device-tree/Bindings/reserved-memory/
H A Dnvidia,tegra210-emc-table.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 EMC Frequency Table
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: On Tegra210, firmware passes a binary representation of the
14 EMC frequency table via a reserved memory region.
17 - $ref: reserved-memory.yaml
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
666 emc: external-memory-controller@2c60000 { global() label
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H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210
966 emc: external-memory-controller@7001b000 { global() label
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #include <dt-bindings/clock/tegra210-car.h>
58 {"nvidia,tegra210-car", 1},
260 /* Initial setup table. */
293 {"emc", NULL, 0, 1},
321 rv = clknode_div_register(sc->clkdom, clks + i); in init_divs()
334 rv = clknode_gate_register(sc->clkdom, clks + i); in init_gates()
347 rv = clknode_mux_register(sc->clkdom, clks + i); in init_muxes()
361 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); in init_fixeds()
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H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
113 /* Post divider <-> register value mapping. */
193 #define DIV_TB(_id, cname, plist, o, s, n, table) \ argument
204 .div_table = table, \
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
603 RD4(sc, sc->base_reg, &reg); in pll_enable()
604 if (sc->type != PLL_E) in pll_enable()
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