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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra20-spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 S/PDIF Controller
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
38 clock-names:
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20
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H A Dnvidia,tegra114-pinmux.txt3 The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
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H A Dnvidia,tegra30-pinmux.txt3 The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
4 as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
9 - compatible: "nvidia,tegra30-pinmux"
10 - reg: Should contain the register physical address and length for each of
14 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16 - nvidia,lock: Integer. Lock the pin configuration against further changes
18 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
20 As with Tegra20, see the Tegra TRM for complete details regarding which groups
25 per-pin mux groups:
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H A Dnvidia,tegra20-pinmux.txt1 NVIDIA Tegra20 pinmux controller
4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
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H A Dnvidia,tegra124-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmu
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H A Dnvidia,tegra124-pinmux.txt3 The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
14 -- third entry - the MIPI_PAD_CTRL register
18 include/dt-binding/pinctrl/pinctrl-tegra.h.
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20
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H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
13 compatible = "compal,paz00", "nvidia,tegra20";
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
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H A Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-binding
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H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-binding
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H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-binding
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H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-binding
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H A Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi"
11 compatible = "compulab,trimslice", "nvidia,tegra20";
20 stdout-path = "serial0:115200n8";
31 vdd-supply = <&hdmi_vdd_reg>;
32 pll-supply = <&hdmi_pll_reg>;
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H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-op
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H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-binding
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H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
6 compatible = "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bu
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H A Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
9 compatible = "nvidia,seaboard", "nvidia,tegra20";
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-suppl
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H A Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
8 model = "NVIDIA Tegra20 Harmony evaluation board";
9 compatible = "nvidia,harmony", "nvidia,tegra20";
18 stdout-path = "serial0:115200n8";
37 hdmi-suppl
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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