Searched +full:tegra20 +full:- +full:mc +full:- +full:gart (Results 1 – 3 of 3) sorted by relevance
1 NVIDIA Tegra20 MC(Memory Controller)4 - compatible : "nvidia,tegra20-mc-gart"5 - reg : Should contain 2 register ranges: physical base address and length of6 the controller's registers and the GART aperture respectively.7 - clocks: Must contain an entry for each entry in clock-names.8 See ../clocks/clock-bindings.txt for details.9 - clock-names: Must include the following entries:10 - mc: the module's clock input11 - interrupts : Should contain MC General interrupt.12 - #reset-cells : Should be 1. This cell represents memory client module ID.[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra20 SoC Memory Controller10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 The Tegra20 Memory Controller merges request streams from various client18 has a configurable arbitration algorithm to allow the user to fine-tune[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra20-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra20750 mc: memory-controller@7000f000 { global() label [all...]