/linux/drivers/hwspinlock/ |
H A D | qcom_hwspinlock.c | 1 // SPDX-License-Identifier: GPL-2.0 10 #include <linux/mfd/syscon.h> 30 struct regmap_field *field = lock->priv; in qcom_hwspinlock_trylock() 47 struct regmap_field *field = lock->priv; in qcom_hwspinlock_unlock() 69 struct regmap_field *field = lock->priv; in qcom_hwspinlock_bust() 75 dev_err(lock->bank->dev, "unable to query spinlock owner\n"); in qcom_hwspinlock_bust() 84 dev_err(lock->bank->dev, "failed to bust spinlock\n"); in qcom_hwspinlock_bust() 140 { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, 141 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, 142 { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, [all …]
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/linux/Documentation/devicetree/bindings/soc/qcom/ |
H A D | qcom,gsbi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 16 representing a serial sub-node device that is mux'd as part of the GSBI 26 const: qcom,gsbi-v1.0.0 28 '#address-cells': 31 cell-index: [all …]
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/linux/Documentation/devicetree/bindings/hwlock/ |
H A D | qcom-hwspinlock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/hwlock/qcom-hwspinlock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 19 - enum: 20 - qcom,sfpb-mutex 21 - qcom,tcsr-mutex 22 - items: 23 - enum: [all …]
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/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-ipq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mfd/qcom-rpm.h> 6 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11 #include <dt-bindings/soc/qcom,gsbi.h> [all …]
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H A D | qcom-apq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 5 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/soc/qcom,gsbi.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> [all …]
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H A D | qcom-apq8084.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/clock/qcom,gcc-apq8084.h> 6 #include <dt-bindings/gpio/gpio.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 13 interrupt-parent = <&intc>; 15 reserved-memory { 16 #address-cells = <1>; [all …]
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H A D | qcom-msm8974.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interconnect/qcom,msm8974.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 10 #include <dt-bindings/gpio/gpio.h> 13 #address-cells = <1>; [all …]
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H A D | qcom-msm8226.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11 #include <dt-bindings/clock/qcom,rpmcc.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 15 - enum: 16 - qcom,sa8775p-pcie-ep 17 - qcom,sdx55-pcie-ep 18 - qcom,sm8450-pcie-ep 19 - items: [all …]
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/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qusb2.c | 1 // SPDX-License-Identifier: GPL-2.0 11 #include <linux/mfd/syscon.h> 13 #include <linux/nvmem-consumer.h> 22 #include <dt-bindings/phy/phy-qcom-qusb2.h> 105 * if yes, then offset gives index in the reg-layout 123 /* set of registers with offsets different per-PH 438 struct regmap *tcsr; global() member [all...] |
H A D | phy-qcom-qmp-usbc.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 13 #include <linux/mfd/syscon.h> 26 #include "phy-qcom-qmp-common.h" 28 #include "phy-qcom-qmp.h" 29 #include "phy-qcom-qmp-pcs-misc-v3.h" 33 /* set of registers with offsets different per-PHY */ 298 /* struct qmp_phy_cfg - per-PHY initialization config */ 302 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 396 "vdda-phy", "vdda-pll", [all …]
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/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | qcom,q6v5.txt | 6 - compatible: 10 "qcom,ipq8074-wcss-pil" 11 "qcom,qcs404-wcss-pil" 13 - reg: 15 Value type: <prop-encoded-array> 19 - reg-names: 24 - interrupts-extended: 26 Value type: <prop-encoded-array> 27 Definition: reference to the interrupts that match interrupt-names 29 - interrupt-names: [all …]
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H A D | qcom,sc7280-adsp-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> 19 - qcom,sc7280-adsp-pil 23 - description: qdsp6ss register 24 - description: efuse q6ss register 28 - description: Phandle to apps_smmu node with sid mask 32 - description: Watchdog interrupt [all …]
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H A D | qcom,msm8916-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Stephan Gerhold <stephan@gerhold.net> 19 - enum: 20 - qcom,msm8909-mss-pil 21 - qcom,msm8916-mss-pil 22 - qcom,msm8953-mss-pil 23 - qcom,msm8974-mss-pil [all …]
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/linux/Documentation/devicetree/bindings/power/avs/ |
H A D | qcom,cpr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Niklas Cassel <nks@flawful.org> 23 - enum: 24 - qcom,qcs404-cpr 25 - const: qcom,cpr 36 - description: Reference clock. 38 clock-names: 40 - const: ref [all …]
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/linux/drivers/clk/ingenic/ |
H A D | tcu.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 10 #include <linux/mfd/ingenic-tcu.h> 11 #include <linux/mfd/syscon.h> 16 #include <dt-bindings/clock/ingenic,tcu.h> 22 #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt 68 const struct ingenic_tcu_clk_info *info = tcu_clk->info; in ingenic_tcu_enable() 69 struct ingenic_tcu *tcu = tcu_clk->tcu; in ingenic_tcu_enable() 71 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); in ingenic_tcu_enable() 79 const struct ingenic_tcu_clk_info *info = tcu_clk->info; in ingenic_tcu_disable() [all …]
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/linux/Documentation/devicetree/bindings/bus/ |
H A D | qcom,ssc-block-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michael Srba <Michael.Srba@seznam.cz> 27 - const: qcom,msm8998-ssc-block-bus 28 - const: qcom,ssc-block-bus 32 - description: SSCAON_CONFIG0 registers 33 - description: SSCAON_CONFIG1 registers 35 reg-names: [all …]
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/linux/drivers/pmdomain/qcom/ |
H A D | cpr.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 24 #include <linux/mfd/syscon.h> 27 #include <linux/nvmem-consumer.h> 29 /* Register Offsets for RB-CPR and Bit Definitions */ 125 #define FUSE_REVISION_UNKNOWN (-1) 237 struct regmap *tcsr; member 254 return !drv->loop_disabled; in cpr_is_allowed() 259 writel_relaxed(value, drv->base + offset); in cpr_write() 264 return readl_relaxed(drv->base + offset); in cpr_read() [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | ipq6018.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11 #include <dt-bindings/clock/qcom,apss-ipq.h> 12 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&intc>; 20 sleep_clk: sleep-clk { [all …]
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H A D | msm8953.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 4 #include <dt-bindings/clock/qcom,gcc-msm8953.h> 5 #include <dt-bindings/clock/qcom,rpmcc.h> 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/soc/qcom,apr.h> 10 #include <dt-bindings/sound/qcom,q6afe.h> 11 #include <dt-bindings/sound/qcom,q6asm.h> 12 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | msm8976.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 9 #include <dt-bindings/clock/qcom,gcc-msm8976.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 14 #include <dt-bindings/power/qcom-rpmpd.h> 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; [all …]
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H A D | msm8998.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/firmware/qcom,scm.h> 10 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/gpio/gpio.h> 14 interrupt-parent = <&intc>; [all …]
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H A D | qcm2290.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 11 #include <dt-bindings/clock/qcom,rpmcc.h> 12 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/firmware/qcom,scm.h> 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #include <dt-bindings/interconnect/qcom,qcm2290.h> [all …]
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H A D | x1e80100.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/interconnect/qcom,icc.h> 14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> [all …]
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H A D | sa8775p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 7 #include <dt-bindings/interconnect/qcom,icc.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 11 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 12 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 13 #include <dt-bindings/dma/qcom-gpi.h> 14 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h> [all …]
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