Searched +full:tcon +full:- +full:ch1 +full:- +full:sclk (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 TCON Channel 0 Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 "#reset-cells":
24 - allwinner,sun4i-a10-tcon-ch0-clk
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun5i.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
74 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
119 .hw.init = CLK_HW_INIT("pll-ddr-base",
126 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
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