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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5
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/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Dutils.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-debu
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H A Dcoex.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2013-2014, 2018-2020, 2022-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
11 #include "iwl-modparam
143 u32 mode; iwl_mvm_send_bt_init_conf() local
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H A Drx.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
10 #include "iwl-tran
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H A Dops.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
15 #include "fw/notif-wai
232 enum ieee80211_smps_mode mode = IEEE80211_SMPS_AUTOMATIC; iwl_mvm_update_link_smps() local
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H A Dtx.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
14 #include "iwl-tran
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H A Drxmq.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-tran
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H A Dmvm.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
26 #include "iwl-o
1084 struct iwl_mvm_tcm tcm; global() member
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H A Ddebugfs-vif.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 struct iwl_dbgfs_pm *dbgfs_pm = &mvmvif->dbgfs_pm; in iwl_dbgfs_update_pm()
20 dbgfs_pm->mask |= param; in iwl_dbgfs_update_pm()
24 int dtimper = vif->bss_conf.dtim_period ?: 1; in iwl_dbgfs_update_pm()
25 int dtimper_msec = dtimper * vif->bss_conf.beacon_int; in iwl_dbgfs_update_pm()
32 dbgfs_pm->keep_alive_seconds = val; in iwl_dbgfs_update_pm()
38 dbgfs_pm->skip_over_dtim = val; in iwl_dbgfs_update_pm()
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H A Dscan.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 #include "iwl-i
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H A Dmac80211.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
25 #include "iwl-dr
5210 iwl_mvm_switch_vif_chanctx_common(struct ieee80211_hw * hw,struct ieee80211_vif_chanctx_switch * vifs,int n_vifs,enum ieee80211_chanctx_switch_mode mode,const struct iwl_mvm_switch_vif_chanctx_ops * ops) iwl_mvm_switch_vif_chanctx_common() argument
5238 iwl_mvm_switch_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif_chanctx_switch * vifs,int n_vifs,enum ieee80211_chanctx_switch_mode mode) iwl_mvm_switch_vif_chanctx() argument
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/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_dbg_values.h2 * Copyright (c) 2017-2018 Cavium, Inc.
253 0x24180000, /* block tcm */
254 0x01460000, /* tcm.init (1 regs) */
255 0x05460010, /* tcm.dbg_select .. tcm.dbg_force_frame (5 regs) */
256 0x02460060, /* tcm.INT_STS_0 .. tcm.INT_MASK_0 (2 regs) */
257 0x02460064, /* tcm.INT_STS_1 .. tcm.INT_MASK_1 (2 regs) */
258 0x02460068, /* tcm.INT_STS_2 .. tcm.INT_MASK_2 (2 regs) */
259 0x01460100, /* tcm.ifen (1 regs) */
260 0x08460109, /* tcm.qm_task_base_evnt_id_0 .. tcm.qm_task_base_evnt_id_7 (8 regs) */
261 0x10460121, /* tcm.qm_agg_task_ctx_part_size_0 .. tcm.qm_sm_task_ctx_ldst_flg_7 (16 regs) */
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H A Dcommon_hsi.h2 * Copyright (c) 2017-2018 Cavium, Inc.
62 … 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/
70 … queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/
71 … of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/
88 * Usually LL2 queues are opened in pairs � TX-RX.
98 // Include firmware verison number only- do not add constants here to avoid redundunt compilations
133 /* possible PFs and VFs - we need a constant for this size */
148 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */
151 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
250 /* TCM agg val selection (HW) */
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H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
52 … 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
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H A Decore_dbg_fw_funcs.c2 * Copyright (c) 2017-2018 Cavium, Inc.
168 return (r[0] < (r[1] - imm[0])); in cond8()
226 * Addresses are in bytes, sizes are in quad-regs.
288 /* Storm Mode definitions */
363 …, val_width, amount) (((val) | ((val) << (val_width))) >> (amount)) & ((1 << (val_width)) - 1)
371 #define FIELD_BIT_MASK(type, field) (((1 << FIELD_BIT_SIZE(type, field)) - 1) << FIELD_DWORD_SHIF…
390 #define NUM_EXTRA_DBG_LINES(block_desc) (1 + (block_desc->has_latency_events ? 1 : 0))
391 #define NUM_DBG_LINES(block_desc) (block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
457 #define MAX_CYCLE_VALUES_MASK ((1 << VALUES_PER_CYCLE) - 1)
909 "tcm", { true, true, true }, true, DBG_TSTORM_ID,
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H A Decore_int.c2 * Copyright (c) 2017-2018 Cavium, Inc.
49 /* This is nasty, but diag is using the drv_dbg_fw_funcs.c [non-ecore flavor],
52 * really optional there would increase], we'll need to re-think this.
134 u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); in ecore_mcp_attn_cb()
136 DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", in ecore_mcp_attn_cb()
138 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, in ecore_mcp_attn_cb()
170 u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID); in ecore_pswhst_attn_cb()
176 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, in ecore_pswhst_attn_cb()
178 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, in ecore_pswhst_attn_cb()
180 …DP_INFO(p_hwfn->p_dev, "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x] Write [0x%02x] Addr … in ecore_pswhst_attn_cb()
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H A Decore_init_values.h2 * Copyright (c) 2017-2018 Cavium, Inc.
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
48 0x00010002, 0x00c60000, /* if mode != '(!asic)&k2', skip 1 ops */
50 0x00010002, 0x00c20000, /* if mode != '(!asic)&e5', skip 1 ops */
52 0x00010002, 0x00be0000, /* if mode != '(!asic)&bb', skip 1 ops */
54 0x00010002, 0x00c60000, /* if mode != '(!asic)&k2', skip 1 ops */
56 0x00010002, 0x00c20000, /* if mode != '(!asic)&e5', skip 1 ops */
61 0x00010002, 0x00190000, /* if mode != 'k2', skip 1 ops */
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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/freebsd/contrib/tcpdump/
H A Dprint-lmp.c21 …ps://web.archive.org/web/20160401194747/http://www.oiforum.com/public/documents/OIF-UNI-01.0.pdf */
25 #include "netdissect-stdinc.h"
39 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
41 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
43 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
93 { 0x08, "Link-Id configuration error"},
94 { 0x10, "Unknown object c-type"},
99 { 0x01, "Unacceptable non-negotiable LINK-SUMMARY parameters"},
100 { 0x02, "Renegotiate LINK-SUMMARY parameters"},
101 { 0x04, "Invalid TE-LINK Object"},
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/freebsd/sys/dev/bxe/
H A Decore_init.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
45 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
216 /* Vnics per mode */
228 /* Vnics per mode */
231 /* COS offset for port1 in E3 B0 4port mode */
253 /* check if queue->COS mapping has changed */ in ecore_map_q_cos()
258 /* update parameters for 4port mode */ in ecore_map_q_cos()
273 /* overwrite queue->VOQ mapping */ in ecore_map_q_cos()
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H A Dbxe.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
64 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
241 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
251 &bxe_debug, 0, "Debug logging mode");
253 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
261 &bxe_queue_count, 0, "Multi-Queue queue count");
288 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
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/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-trans.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
15 #include "iwl-debu
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/freebsd/share/misc/
H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2024-12-04 20:34:02
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
62 0200 TP-Link
81 120e ASI120MC-S Planetary Camera
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