Searched +full:system +full:- +full:controller0 (Results 1 – 5 of 5) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 * Marvell Armada CP110 System Controller7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>14 * - PLL0 (1 Ghz)15 * - PPv2 core (1/3 PLL0)16 * - x2 Core (1/2 PLL0)17 * - Core (1/2 x2 Core)18 * - SDIO (2/5 PLL0)20 * - NAND clock, which is either:21 * - Equal to SDIO clock[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Mobileye EyeQ7H SoC system controller10 - Benoît Monin <benoit.monin@bootlin.com>11 - Grégory Clement <gregory.clement@bootlin.com>12 - Théo Lebrun <theo.lebrun@bootlin.com>13 - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>16 OLB ("Other Logic Block") is a hardware system controller grouping[all …]
15 /dts-v1/;18 #address-cells = <2>;19 #size-cells = <1>;22 dcr-parent = <&{/cpus/cpu@0}>;34 #address-cells = <1>;35 #size-cells = <0>;41 clock-frequency = <0>; /* Filled in by zImage */42 timebase-frequency = <0>; /* Filled in by zImage */43 i-cache-line-size = <32>;44 d-cache-line-size = <32>;[all …]
11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <1>;18 dcr-parent = <&{/cpus/cpu@0}>;30 #address-cells = <1>;31 #size-cells = <0>;37 clock-frequency = <0>; /* Filled in by U-Boot */38 timebase-frequency = <0>; /* Filled in by U-Boot */39 i-cache-line-size = <32>;40 d-cache-line-size = <32>;[all …]