| /freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/ |
| H A D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctr
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| /freebsd/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | ti,sci.txt | 1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
6 management of the System on Chip (SoC) system. These include various system
9 An example of such an SoC is K2G, which contains the system control hardware
10 block called Power Management Micro Controller (PMMC). This hardware block is
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
27 - compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
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|
| /freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/ |
| H A D | hisilicon.txt | 2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3670";
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
21 - compatible = "hisilicon,hi3798cv200";
25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
29 - compatible = "hisilicon,hi3620-hi4511";
33 - compatible = "hisilicon,hi6220";
37 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
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|
| /freebsd/share/doc/smm/02.config/ |
| H A D | 5.t | 34 sample VAX-11/780 system on which the hardware can be
36 We then study the rules needed to configure a VAX-11/750
39 VAX-11/780 System
41 Our VAX-11/780 is configured with hardware
43 (this is one of the high-end configurations).
53 MASSBUS controller Emulex nexus ? mba0 hp(4)
56 MASSBUS controller Emulex nexus ? mba1
60 tape controller Emulex uba0 tm0 tm(4)
69 Table 1. VAX-11/780 Hardware support.
77 is ``vax''. We will assume this system will
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|
| H A D | 4.t | 40 configuration parameters global to all system images
44 system image to be generated, and
51 cpu types, options, timezone, system identifier, and maximum users.
55 The system is to run on the machine type specified. No more than
63 This system is to run on the cpu type specified.
76 Compile the listed optional code into the system.
80 \-DFUNNY \-DHAHA in the resultant makefile.
89 Other kernel options controlling system sizes and limits
97 Options that are used within the system makefile
108 Specifies the timezone used by the system. This is measured in the
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|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
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|
| /freebsd/sys/contrib/device-tree/Bindings/arm/marvell/ |
| H A D | mvebu-system-controller.txt | 1 MVEBU System Controller
2 -----------------------
7 - compatible: one of:
8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
|
| H A D | ap80x-system-controller.txt | 1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
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|
| /freebsd/usr.sbin/mlxcontrol/ |
| H A D | mlxcontrol.8 | 29 .Nd Mylex DAC-family RAID management utility
40 .Ar controller
41 .Op Ar controller ...
54 .Ar controller
67 Controller names are of the form "mlxN"
68 where N is the unit number of the controller.
72 .Bl -tag -width rebuild
74 Print the status of controllers and system drives.
78 about all controllers and drives in the system.
90 Rescan one or more controllers for non-attached system drives
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|
| /freebsd/share/man/man4/man4.arm/ |
| H A D | aw_syscon.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
32 .Nd driver for the system controller in Allwinner SoC
36 device driver provides support for the Allwinner system controller.
37 This controller provides registers for tying together related functionality in a
44 driver supports the system controller with one of the following compatible
47 .Bl -bullet -compact
49 allwinner,sun50i-a64-system-controller
51 allwinner,sun50i-a64-system-control
53 allwinner,sun8i-a83t-system-controller
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|
| /freebsd/share/man/man4/ |
| H A D | mlx.4 | 31 .Nd Mylex DAC-family RAID driver
36 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
50 driver provides support for Mylex DAC-family PCI to SCSI RAID controllers,
57 .Bl -bullet -compact
79 RAIDarray 230 controllers, aka the Ultra-SCSI DEC KZPAC-AA (1-ch, 4MB
80 cache), KZPAC-CA (3-ch, 4MB), KZPAC-CB (3-ch, 8MB cache)
85 available for the controller.
90 .Ss Controller initialisation phase
91 .Bl -diag
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|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | ti,sci-inta.txt | 5 which handles the termination of system events to that they can
6 be coherently processed by the host(s) in the system. A maximum
11 +-----------------------------------------+
13 | +--------------+ +------------+ |
14 m ------>| | vint | bit | | 0 |.....|63| vint0 |
15 . | +--------------+ +------------+ | +------+
17 Globalevents ------>| . . |------>| IRQ |
19 . | . . | +------+
20 n ------>| +--------------+ +------------+ |
22 | +--------------+ +------------+ |
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|
| H A D | ti,sci-inta.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in the system. A maximum
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
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|
| H A D | ti,sci-intr.txt | 10 +----------------------+
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
19 | +------+ | N | |
20 | | irqM | +-----+ |
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|
| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-rese
[all...] |
| H A D | ti,sci-reset.txt | 1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
4 Some TI SoCs contain a system controller (like the Power Management Micro
5 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
7 between the host processor running an OS and the system controller happens
8 through a protocol called TI System Control Interface (TI-SCI protocol).
12 TI-SCI Reset Controller Node
14 This reset controller node uses the TI SCI protocol to perform the reset
16 node of the associated TI-SCI system controller node.
19 --------------------
20 - compatible : Should be "ti,sci-reset"
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|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
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|
| H A D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Controller Registers R/W
10 System controlle
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| /freebsd/sys/contrib/device-tree/Bindings/arm/socionext/ |
| H A D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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|
| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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|
| /freebsd/sys/contrib/device-tree/Bindings/sram/ |
| H A D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
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|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-cl
[all...] |
| H A D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
21 co-processor), audio, and several peripherals.
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|
| /freebsd/stand/efi/include/ |
| H A D | efipciio.h | 3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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|