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/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
22 "syscon"
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/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
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H A Dhix5hd2-phy.txt1 Hisilicon hix5hd2 SATA PHY
2 -----------------------
5 - compatible: should be "hisilicon,hix5hd2-sata-phy"
6 - reg: offset and length of the PHY registers
7 - #phy-cells: must be 0
8 Refer to phy/phy-bindings.txt for the generic PHY binding properties
11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
13 register of controlling sata power supply.
16 sata_phy: phy@f9900000 {
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H A Dti,omap-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP USB2 PHY
10 - Kishon Vijay Abraham I <kishon@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - items:
17 - enum:
18 - ti,dra7x-usb2
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H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
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H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
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H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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H A Dbrcm,brcmstb-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB USB PHY
9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
12 - Al Cooper <alcooperx@gmail.com>
13 - Rafał Miłecki <rafal@milecki.pl>
18 - brcm,bcm4908-usb-phy
19 - brcm,bcm7211-usb-phy
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H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
28 power-domains:
37 '#phy-cells':
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
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H A Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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H A Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
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H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
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H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
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H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
18 g3dsys: syscon@13000000 {
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
21 "syscon";
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
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/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
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H A Dti,am62-usb.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
19 - description: USB CFG register space
20 - description: USB PHY2 register space
24 power-domains:
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
66 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg); in csiphy_routing_cfg_3630()
69 static void csiphy_routing_cfg_3430(struct isp_csiphy *phy, u32 iface, bool on, in csiphy_routing_cfg_3430() argument
80 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, 0); in csiphy_routing_cfg_3430()
87 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, csirxfe); in csiphy_routing_cfg_3430()
91 * Configure OMAP 3 CSI PHY routing.
92 * @phy: relevant phy device
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/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
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