/linux/Documentation/devicetree/bindings/soc/starfive/ |
H A D | starfive,jh7110-syscon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - William Qiu <william.qiu@starfivetech.com> 19 - items: 20 - const: starfive,jh7110-sys-syscon 21 - const: syscon 22 - const: simple-mfd 23 - items: [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | starfive,jh7110-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Minda Chen <minda.chen@starfivetech.com> 14 const: starfive,jh7110-pcie-phy 19 "#phy-cells": 22 starfive,sys-syscon: 23 $ref: /schemas/types.yaml#/definitions/phandle-array 25 - items: [all …]
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H A D | nuvoton,ma35d1-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/nuvoton,ma35d1-usb2-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hui-Ping Chen <hpchen0nvt@gmail.com> 15 - nuvoton,ma35d1-usb2-phy 17 "#phy-cells": 23 nuvoton,sys: 26 phandle to syscon for checking the PHY clock status. 29 - compatible [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linusw@kernel.org> 25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to 26 different values and sometimes also hard-wires the output divider. They 38 integratorap-cm 41 integratorap-sys 44 integratorap-pci 14 1 14 [all …]
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H A D | pistachio-clock.txt | 6 from the device-tree. 9 ---------------- 12 defined with the following clock-output-names: 13 - "xtal": External 52Mhz oscillator (required) 14 - "audio_clk_in": Alternate audio reference clock (optional) 15 - "enet_clk_in": Alternate ethernet PHY clock (optional) 18 ---------------------- 21 co-processor), audio, and several peripherals. 24 - compatible: Must be "img,pistachio-clk". 25 - reg: Must contain the base address and length of the core clock controller. [all …]
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H A D | mediatek,mt8192-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 19 - enum: 20 - mediatek,mt8192-topckgen 21 - mediatek,mt8192-infracfg 22 - mediatek,mt8192-pericfg 23 - mediatek,mt8192-apmixedsys [all …]
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H A D | mediatek,mt8195-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 14 PLLs --> 15 dividers --> 17 --> 27 - enum: 28 - mediatek,mt8195-topckgen [all …]
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H A D | starfive,jh7110-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 registers in the sys syscon. So the PLLs node should be a child of 13 SYS-SYSCON node. 18 - Xingyu Wu <xingyu.wu@starfivetech.com> 22 const: starfive,jh7110-pll 28 '#clock-cells': 31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. [all …]
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H A D | mediatek,mt8186-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 14 PLLs --> 15 dividers --> 17 --> 29 - enum: 30 - mediatek,mt8186-mcusys [all …]
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H A D | mediatek,mt8365-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Markus Schneider-Pargmann <msp@baylibre.com> 20 - enum: 21 - mediatek,mt8365-topckgen 22 - mediatek,mt8365-infracfg 23 - mediatek,mt8365-apmixedsys 24 - mediatek,mt8365-pericfg [all …]
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H A D | mediatek,mt8188-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Garmin Chang <garmin.chang@mediatek.com> 14 PLLs --> 15 dividers --> 17 --> 29 - enum: 30 - mediatek,mt8188-apmixedsys [all …]
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/linux/Documentation/devicetree/bindings/spi/ |
H A D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mark Brown <broonie@kernel.org> 13 - $ref: spi-controller.yaml# 14 - if: 19 - mscc,ocelot-spi 20 - mscc,jaguar2-spi 25 - if: [all …]
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/linux/drivers/phy/starfive/ |
H A D | phy-jh7110-usb.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include <linux/mfd/syscon.h> 40 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive() 41 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive() 47 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive() 61 return -EINVAL; in usb2_phy_set_mode() 64 if (mode != phy->mode) { in usb2_phy_set_mode() 65 dev_dbg(&_phy->dev, "Changing phy to %d\n", mode); in usb2_phy_set_mode() 66 phy->mode = mode; in usb2_phy_set_mode() 71 regmap_update_bits(phy->sys_syscon, SYSCON_USB_SPLIT_OFFSET, in usb2_phy_set_mode() [all …]
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/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3588-extra.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "rk3588-base.dtsi" 7 #include "rk3588-extra-pinctrl.dtsi" 11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 16 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 19 phy-names = "usb2-phy", "usb3-phy"; 21 power-domains = <&power RK3588_PD_USB>; 24 snps,dis-u2-freeclk-exists-quirk; 25 snps,dis-del-phy-power-chg-quirk; 26 snps,dis-tx-ipgap-linecheck-quirk; [all …]
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H A D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "rk356x-base.dtsi" 11 cpu0_opp_table: opp-table-0 { 12 compatible = "operating-points-v2"; 13 opp-shared; 15 opp-408000000 { 16 opp-hz = /bits/ 64 <408000000>; 17 opp-microvolt = <850000 850000 1150000>; 18 clock-latency-ns = <40000>; 21 opp-600000000 { [all …]
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/linux/drivers/clk/at91/ |
H A D | clk-system.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk-provider.h> 10 #include <linux/mfd/syscon.h> 43 struct clk_system *sys = to_clk_system(hw); in clk_system_prepare() local 45 regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); in clk_system_prepare() 47 if (!is_pck(sys->id)) in clk_system_prepare() 50 while (!clk_system_ready(sys->regmap, sys->id)) in clk_system_prepare() 58 struct clk_system *sys = to_clk_system(hw); in clk_system_unprepare() local 60 regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); in clk_system_unprepare() 65 struct clk_system *sys = to_clk_system(hw); in clk_system_is_prepared() local [all …]
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/linux/drivers/mfd/ |
H A D | altera-sysmgr.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2018-2019, Intel Corporation. 7 * Based on syscon driver. 10 #include <linux/arm-smccc.h> 13 #include <linux/mfd/altera-sysmgr.h> 14 #include <linux/mfd/syscon.h> 22 * struct altr_sysmgr - Altera SOCFPGA System Manager 108 return ERR_PTR(-ENODEV); in altr_sysmgr_regmap_lookup_by_phandle() 116 return ERR_PTR(-EPROBE_DEFER); in altr_sysmgr_regmap_lookup_by_phandle() 120 return sysmgr->regmap; in altr_sysmgr_regmap_lookup_by_phandle() [all …]
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/linux/drivers/clk/versatile/ |
H A D | clk-icst.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 * Copyright (C) 2012-2015 Linus Walleij 17 #include <linux/clk-provider.h> 20 #include <linux/mfd/syscon.h> 23 #include "clk-icst.h" 37 * struct clk_icst - ICST VCO clock wrapper 59 * vco_get() - get ICST VCO settings from a certain ICST 68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get() 77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get() 78 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. in vco_get() [all …]
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/linux/Documentation/devicetree/bindings/timer/ |
H A D | img,pistachio-gptimer.txt | 1 * Pistachio general-purpose timer based clocksource 4 - compatible: "img,pistachio-gptimer". 5 - reg: Address range of the timer registers. 6 - interrupts: An interrupt for each of the four timers 7 - clocks: Should contain a clock specifier for each entry in clock-names 8 - clock-names: Should contain the following entries: 9 "sys", interface clock 12 - img,cr-periph: Must contain a phandle to the peripheral control 13 syscon node. 17 compatible = "img,pistachio-gptimer"; [all …]
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/linux/Documentation/devicetree/bindings/pwm/ |
H A D | img-pwm.txt | 4 - compatible: Should be "img,pistachio-pwm" 5 - reg: Should contain physical base address and length of pwm registers. 6 - clocks: Must contain an entry for each entry in clock-names. 7 See ../clock/clock-bindings.txt for details. 8 - clock-names: Must include the following entries. 9 - pwm: PWM operating clock. 10 - sys: PWM system interface clock. 11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the 13 - img,cr-periph: Must contain a phandle to the peripheral control 14 syscon node which contains PWM control registers. [all …]
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/linux/Documentation/devicetree/bindings/power/ |
H A D | amlogic,meson-gx-pwrc.txt | 7 ---------------- 13 power-domain.yaml 16 --------------------- 19 - compatible: should be one of the following : 20 - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs 21 - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs 22 - #power-domain-cells: should be 0 23 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node 24 - resets: phandles to the reset lines needed for this power demain sequence 26 - clocks: from common clock binding: handle to VPU and VAPB clocks [all …]
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/linux/Documentation/devicetree/bindings/dma/ |
H A D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC) 4 - compatible: Must be "img,pistachio-mdc-dma". 5 - reg: Must contain the base address and length of the MDC registers. 6 - interrupts: Must contain all the per-channel DMA interrupts. 7 - clocks: Must contain an entry for each entry in clock-names. 8 See ../clock/clock-bindings.txt for details. 9 - clock-names: Must include the following entries: 10 - sys: MDC system interface clock. 11 - img,cr-periph: Must contain a phandle to the peripheral control syscon 13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier. [all …]
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/linux/arch/mips/boot/dts/mscc/ |
H A D | ocelot.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 #address-cells = <1>; 6 #size-cells = <1>; 10 #address-cells = <1>; 11 #size-cells = <0>; 25 cpuintc: interrupt-controller { 26 #address-cells = <0>; 27 #interrupt-cells = <1>; 28 interrupt-controller; 29 compatible = "mti,cpu-interrupt-controller"; [all …]
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/linux/arch/mips/boot/dts/img/ |
H A D | pistachio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/pistachio-clk.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #include <dt-bindings/reset/pistachio-resets.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 22 #address-cells = <1>; [all …]
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/linux/drivers/soc/rockchip/ |
H A D | grf.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/mfd/syscon.h> 33 * clock-framework and the mmc controllers making them unreliable. 162 .compatible = "rockchip,rk3036-grf", 165 .compatible = "rockchip,rk3128-grf", 168 .compatible = "rockchip,rk3228-grf", 171 .compatible = "rockchip,rk3288-grf", 174 .compatible = "rockchip,rk3328-grf", 177 .compatible = "rockchip,rk3368-grf", 180 .compatible = "rockchip,rk3399-grf", [all …]
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