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Searched +full:synquacer +full:- +full:spi (Results 1 – 15 of 15) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer External Interrupt Unit (EXIU)
10 - Ard Biesheuvel <ardb@kernel.org>
13 The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
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H A Dsocionext,synquacer-exiu.txt1 Socionext SynQuacer External Interrupt Unit (EXIU)
3 The Socionext Synquacer SoC has an external interrupt unit (EXIU)
5 level-high type GICv3 SPIs.
9 - compatible : Should be "socionext,synquacer-exiu".
10 - reg : Specifies base physical address and size of the
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
20 - Only SPIs can use the EXIU as an interrupt parent.
24 exiu: interrupt-controller@510c0000 {
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H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsocionext,synquacer-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer HS-SPI Controller
10 - Masahisa Kojima <masahisa.kojima@linaro.org>
11 - Jassi Brar <jaswinder.singh@linaro.org>
14 - $ref: spi-controller.yaml#
18 const: socionext,synquacer-spi
26 - description: core clock
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H A Dspi-synquacer.txt1 * Socionext Synquacer HS-SPI bindings
4 - compatible: should be "socionext,synquacer-spi"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts.
8 - clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK)
9 - clock-names: Shall be "iHCLK" and "iPCLK" respectively
12 - socionext,use-rtm: boolean, if required to use "retimed clock" for RX
13 - socionext,set-aces: boolean, if same active clock edges field to be set.
17 spi0: spi@ff110000 {
18 compatible = "socionext,synquacer-spi";
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
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H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
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H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
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