Searched +full:synquacer +full:- +full:pre +full:- +full:its (Results 1 – 11 of 11) sorted by relevance
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Copyright 2020-2022 Advanced Micro Devices, Inc.6 #include <dt-bindings/gpio/gpio.h>7 #include "dt-bindings/interrupt-controller/arm-gic.h"11 compatible = "amd,pensando-elba";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <2>;16 dma-coherent;19 compatible = "fixed-clock";[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <maz@kernel.org>15 Software Generated Interrupts (SGI), and Locality-specific Peripheral19 - $ref: /schemas/interrupt-controller.yaml#24 - items:25 - enum:26 - qcom,msm8996-gic-v3[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "mmio-sram";12 #address-cells = <1>;13 #size-cells = <1>;17 gic500: interrupt-controller@1800000 {18 compatible = "arm,gic-v3";19 #address-cells = <2>;20 #size-cells = <2>;22 #interrupt-cells = <3>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "mmio-sram";12 #address-cells = <1>;13 #size-cells = <1>;17 gic500: interrupt-controller@1800000 {18 compatible = "arm,gic-v3";25 #address-cells = <2>;26 #size-cells = <2>;28 #interrupt-cells = <3>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "mmio-sram";11 #address-cells = <1>;12 #size-cells = <1>;15 gic500: interrupt-controller@1800000 {16 compatible = "arm,gic-v3";17 #address-cells = <2>;18 #size-cells = <2>;20 #interrupt-cells = <3>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy-am654-serdes.h>11 compatible = "mmio-sram";13 #address-cells = <1>;14 #size-cells = <1>;17 atf-sram@0 {21 sysfw-sram@f0000 {25 l3cache-sram@100000 {30 gic500: interrupt-controller@1800000 {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-ti.h>12 serdes_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;21 compatible = "mmio-sram";23 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/9 serdes_refclk: serdes-refclk {10 #clock-cells = <0>;11 compatible = "fixed-clock";17 compatible = "mmio-sram";19 #address-cells = <1>;20 #size-cells = <1>;23 atf-sram@0 {28 scm_conf: scm-conf@100000 {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-ti.h>12 serdes_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;21 compatible = "mmio-sram";23 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/phy/phy.h>10 #include <dt-bindings/phy/phy-ti.h>12 #include "k3-serdes.h"15 serdes_refclk: clock-serdes {16 #clock-cells = <0>;17 compatible = "fixed-clock";25 compatible = "mmio-sram";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/phy/phy-ti.h>9 #include <dt-bindings/mux/mux.h>11 #include "k3-serdes.h"14 cmn_refclk: clock-cmnrefclk {15 #clock-cells = <0>;16 compatible = "fixed-clock";17 clock-frequency = <0>;[all …]