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Searched +full:synquacer +full:- +full:exiu (Results 1 – 2 of 2) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer External Interrupt Unit (EXIU)
10 - Ard Biesheuvel <ardb@kernel.org>
13 The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
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/linux/drivers/irqchip/
H A Dirq-sni-exiu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Socionext External Interrupt Unit (EXIU)
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
69 writel_relaxed(val, data->base + EIMASK); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
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