Home
last modified time | relevance | path

Searched +full:sync +full:- +full:mode (Results 1 – 25 of 1081) sorted by relevance

12345678910>>...44

/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
15 # Sync Width 3.813 us 0.064 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
40 # Sync Width 2.032 us 0.080 ms
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
61 # Sync Width 1.556 us 0.069 ms
73 mode "640x480-85"
[all …]
/linux/include/drm/
H A Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
46 * enum drm_mode_status - hardware support status of a mode
47 * @MODE_OK: Mode OK
50 * @MODE_H_ILLEGAL: mode has illegal horizontal timings
51 * @MODE_V_ILLEGAL: mode has illegal vertical timings
53 * @MODE_NOMODE: no mode with a matching name
54 * @MODE_NO_INTERLACE: interlaced mode not supported
55 * @MODE_NO_DBLESCAN: doublescan mode not supported
56 * @MODE_NO_VSCAN: multiscan mode not supported
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-offsets.h>
15 /* Do nothing if not running in HV mode */
28 sync
31 sync
34 sync
37 sync
41 li r3,0x1200 /* enable i-fetch cacheability */
50 sync
71 /* Do nothing if not running in HV mode */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6dsp-lpass-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - qcom,q6afe-dais
20 '#sound-dai-cells':
23 '#address-cells':
26 '#size-cells':
31 '^dai@[0-9]+$':
[all …]
/linux/io_uring/
H A Dsync.c1 // SPDX-License-Identifier: GPL-2.0
15 #include "sync.h"
22 int mode; member
27 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); in io_sfr_prep() local
29 if (unlikely(sqe->addr || sqe->buf_index || sqe->splice_fd_in)) in io_sfr_prep()
30 return -EINVA in io_sfr_prep()
42 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); io_sync_file_range() local
55 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); io_fsync_prep() local
72 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); io_fsync() local
87 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); io_fallocate_prep() local
101 struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); io_fallocate() local
[all...]
/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
109 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
124 #define SYNC_ENAB 0 /* Sync Modes Enable */
130 #define MONSYNC 0 /* 8 Bit Sync character */
131 #define BISYNC 0x10 /* 16 bit sync character */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
[all …]
/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
32 (Note: Choosing the 56channel mode for transmission or as
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
[all …]
/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define SITMDR1 0x00 /* Transmit Mode Register 1 */
9 #define SITMDR2 0x04 /* Transmit Mode Register 2 */
10 #define SITMDR3 0x08 /* Transmit Mode Register 3 */
11 #define SIRMDR1 0x10 /* Receive Mode Register 1 */
12 #define SIRMDR2 0x14 /* Receive Mode Register 2 */
13 #define SIRMDR3 0x18 /* Receive Mode Register 3 */
28 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
29 #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
30 #define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */
[all …]
/linux/drivers/net/ethernet/xscale/
H A Dixp46x_ts.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 u32 control; /* 0x00 Time Sync Control Register */
27 u32 event; /* 0x04 Time Sync Event Register */
28 u32 addend; /* 0x08 Time Sync Addend Register */
29 u32 accum; /* 0x0C Time Sync Accumulator Register */
30 u32 test; /* 0x10 Time Sync Test Register */
38 u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
39 u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
40 u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
41 u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
[all …]
/linux/tools/testing/selftests/arm64/mte/
H A Dcheck_hugetlb_options.c1 // SPDX-License-Identifier: GPL-2.0
94 static int check_child_tag_inheritance(char *ptr, int size, int mode) in check_child_tag_inheritance() argument
103 if (child == -1) { in check_child_tag_inheritance()
107 mte_initialize_current_context(mode, (uintptr_t)ptr, size); in check_child_tag_inheritance()
135 static int check_mte_memory(char *ptr, int size, int mode, int tag_check) in check_mte_memory() argument
137 mte_initialize_current_context(mode, (uintptr_t)ptr, size); in check_mte_memory()
146 static int check_hugetlb_memory_mapping(int mem_type, int mode, int mapping, int tag_check) in check_hugetlb_memory_mapping() argument
154 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); in check_hugetlb_memory_mapping()
159 mte_initialize_current_context(mode, (uintptr_t)map_ptr, map_size); in check_hugetlb_memory_mapping()
167 result = check_mte_memory(ptr, map_size, mode, tag_check); in check_hugetlb_memory_mapping()
[all …]
H A Dcheck_buffer_fill.c1 // SPDX-License-Identifier: GPL-2.0
17 1, 555, 1033, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE,
18 /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0
28 static int check_buffer_by_byte(int mem_type, int mode) in check_buffer_by_byte() argument
34 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); in check_buffer_by_byte()
41 mte_initialize_current_context(mode, (uintptr_t)ptr, sizes[i]); in check_buffer_by_byte()
63 static int check_buffer_underflow_by_byte(int mem_type, int mode, in check_buffer_underflow_by_byte() argument
71 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); in check_buffer_underflow_by_byte()
80 mte_initialize_current_context(mode, (uintptr_t)ptr, -underflow_range); in check_buffer_underflow_by_byte()
83 for (j = sizes[i] - 1; (j >= -underflow_range) && in check_buffer_underflow_by_byte()
[all …]
H A Dcheck_user_mem.c1 // SPDX-License-Identifier: GPL-2.0
34 static int check_usermem_access_fault(int mem_type, int mode, int mapping, in check_usermem_access_fault() argument
47 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); in check_usermem_access_fault()
49 if (fd == -1) in check_usermem_access_fault()
60 mte_initialize_current_context(mode, (uintptr_t)ptr, len); in check_usermem_access_fault()
74 tag_len = len - tag_offset; in check_usermem_access_fault()
114 * Accessing user memory in kernel with invalid tag should fail in sync in check_usermem_access_fault()
115 * mode without fault but may not fail in async mode as per the in check_usermem_access_fault()
121 if (mode == MTE_SYNC_ERR && syscall_len < len) { in check_usermem_access_fault()
123 } else if (mode == MTE_ASYNC_ERR && syscall_len == size) { in check_usermem_access_fault()
[all …]
H A Dcheck_tags_inclusion.c1 // SPDX-License-Identifier: GPL-2.0
22 static int verify_mte_pointer_validity(char *ptr, int mode) in verify_mte_pointer_validity() argument
24 mte_initialize_current_context(mode, (uintptr_t)ptr, BUFFER_SIZE); in verify_mte_pointer_validity()
29 ksft_print_msg("Unexpected fault recorded for %p-%p in mode %x\n", in verify_mte_pointer_validity()
30 ptr, ptr + BUFFER_SIZE, mode); in verify_mte_pointer_validity()
36 mte_initialize_current_context(mode, (uintptr_t)ptr, BUFFER_SIZE + 1); in verify_mte_pointer_validity()
41 ksft_print_msg("No valid fault recorded for %p in mode %x\n", in verify_mte_pointer_validity()
42 ptr, mode); in verify_mte_pointer_validity()
49 static int check_single_included_tags(int mem_type, int mode) in check_single_included_tags() argument
60 ret = mte_switch_mode(mode, MT_INCLUDE_VALID_TAG(tag), false); in check_single_included_tags()
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_drm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) ST-Ericsson SA 2013
52 /* One-shot mode: flow stops after one frame */
54 /* Command mode with tearing effect (TE) IRQ sync */
57 * Command mode with bus turn-around (BTA) and tearing effect
58 * (TE) IRQ sync.
61 /* Video mode with tearing effect (TE) sync IRQ */
63 /* Video mode with the formatter itself as sync source */
65 /* DPI video with the formatter itsels as sync source */
102 return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW || in mcde_flow_is_video()
[all …]
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
96 * In oneshot mode we do not send continuous updates in mcde_display_irq()
101 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
[all …]
/linux/Documentation/networking/
H A Dipvs-sysctl.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IPvs-sysctl
10 am_droprate - INTEGER
13 It sets the always mode drop rate, which is used in the mode 3
16 amemthresh - INTEGER
25 backup_only - BOOLEAN
26 - 0 - disabled (default)
27 - not 0 - enabled
30 in backup mode to avoid packet loops for DR/TUN methods.
32 conn_reuse_mode - INTEGER
[all …]
/linux/arch/mips/alchemy/common/
H A Dsleeper.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Sleep helper for Au1xxx sleep mode.
74 sync
76 sync
103 sync
105 sync
107 sync
129 sync
131 sync
133 /* wait for sdram to enter self-refresh mode */
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
[all …]
/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16475.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16475.pdf
19 - adi,adis16475-1
20 - adi,adis16475-2
21 - adi,adis16475-3
22 - adi,adis16477-1
23 - adi,adis16477-2
[all …]
/linux/Documentation/sound/soc/
H A Ddai.rst35 I2S has several different operating modes:-
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
54 while sync runs at the sample rate. PCM also supports Time Division
56 is sometimes referred to as network mode).
58 Common PCM operating modes:-
60 Mode A
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
63 Mode B
64 MSB is transmitted on rising edge of FRAME/SYNC.
/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
40 In synchronous mode, all channels are updated at the beginning of the PWM period,
[all …]

12345678910>>...44