Home
last modified time | relevance | path

Searched +full:super +full:- +full:speed (Results 1 – 25 of 139) sorted by relevance

123456

/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
[all …]
H A Dgeneric.txt4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed-plus",
6 "super-speed", "high-speed", "full-speed" and
7 "low-speed". In case this isn't passed via DT, USB
10 - dr_mode: tells Dual-Role USB controllers that we want to work on a
15 - phy_type: tells USB controllers that we want to configure the core to support
16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
20 - otg-rev: tells usb driver the release number of the OTG and EH supplement
22 in binary-coded decimal (i.e. 2.0 is 0200H). This
24 is enabled, if ADP is required, otg-rev should be
[all …]
H A Dusb-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
16 mode-switch:
20 orientation-switch:
24 retimer-switch:
40 Super Speed (SS) Output endpoint to the Type-C connector
43 $ref: /schemas/graph.yaml#/$defs/port-base
[all …]
H A Dnxp,ptn36502.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PTN36502 Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver
10 - Luca Weiss <luca.weiss@fairphone.com>
15 - nxp,ptn36502
20 vdd18-supply:
23 orientation-switch: true
24 retimer-switch: true
31 description: Super Speed (SS) Output endpoint to the Type-C connector
[all …]
H A Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
24 orientation-switch: true
25 retimer-switch: true
[all …]
H A Dti,hd3ss3220.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
12 description: |-
14 Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The
36 description: Super Speed (SS) MUX inputs connected to SS capable connector.
40 description: Output of 2:1 MUX connected to Super Speed (SS) data bus.
43 - port@0
44 - port@1
[all …]
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
23 - nvidia,tegra186-xudc # For Tegra186
[all …]
H A Dcdns-usb3.txt1 Binding for the Cadence USBSS-DRD controller
4 - reg: Physical base address and size of the controller's register areas.
6 - HOST registers area
7 - DEVICE registers area
8 - OTG/DRD registers area
9 - reg-names - register memory area names:
10 "xhci" - for HOST registers space
11 "dev" - for DEVICE registers space
12 "otg" - for OTG/DRD registers space
13 - compatible: Should contain: "cdns,usb3"
[all …]
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
[all …]
/freebsd/share/man/man4/
H A Dncthwm.47 .Nd Hardware monitoring controller on Nuvoton Super I/Os
15 Super I/O chips. It expose fan speed via
23 .Bl -bullet -compact
27 Nuvoton NCT6796D-E
31 These variables are available as read-only
34 .Bl -tag -width indent
36 CPU fan speed in RPM.
38 System fan speed in RPM.
40 AUX0 fan speed in RPM.
42 AUX1 fan speed in RPM.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-binding
[all...]
/freebsd/share/doc/smm/05.fastfs/
H A D3.t35 A file system is described by its super-block,
37 Because the super-block contains critical data,
40 since the super-block data does not change,
42 or other hard disk error causes the default super-block
53 file system's super-block
66 that includes a redundant copy of the super-block,
84 could cause the loss of all redundant copies of the super-block.
92 or platter can be lost without losing all copies of the super-block.
99 out with its super-block at the ``known'' location,
136 systems that has roughly 1.2 gigabytes of on-line storage.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-usb3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
13 assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
17 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
20 phy-names = "usb3-phy";
24 maximum-speed = "super-speed";
25 snps,dis-u1-entry-quirk;
26 snps,dis-u2-entry-quirk;
H A Dk3-am642-hummingboard-t-usb3.dtso1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
5 * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1.
8 /dts-v1/;
11 #include <dt-bindings/phy/phy.h>
13 #include "k3-serdes.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
21 cdns,num-lanes = <1>;
22 cdns,phy-type = <PHY_TYPE_USB3>;
[all …]
H A Dk3-am6548-iot2050-advanced-m2-bkey-usb3.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
4 * Copyright (c) Siemens AG, 2022-2024
11 /dts-v1/;
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/gpio/gpio.h>
18 assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&minipcie_pins_default>;
29 num-lanes = <1>;
[all …]
H A Dk3-am654-pcie-usb3.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
14 #include "k3-pinctrl.h"
21 num-lanes = <1>;
23 phy-names = "pcie-phy0";
24 reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
[all …]
/freebsd/sys/dev/usb/
H A Dusb.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
80 #define USB_FRAMES_PER_SECOND_FS 1000 /* full speed */
81 #define USB_FRAMES_PER_SECOND_HS 8000 /* high speed */
114 /* Allow for marginal and non-conforming devices. */
135 * - USB config 0
136 * - USB interfaces
137 * - USB alternative interfaces
138 * - USB endpoints
140 * - USB config 1
[all …]

123456