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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks
32 * SSPP sub-blocks/features
34 …* @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEE…
37 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
68 * MIXER sub-blocks/features
69 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
78 * DSPP sub-blocks
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/linux/arch/arm64/crypto/
H A Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
49 * int blocks)
51 * int blocks)
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
92 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
96 st1 {v0.16b-v3.16b}, [x0], #64
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H A Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
149 ld1 {HH.2d-HH4.2d}, [x8]
197 // PMULL (64x64->128) based reduction for CPUs that can do
214 // 64x64->128 PMULL instruction
253 tbnz w0, #0, 2f // skip until #blocks is a
256 1: ld1 {XM3.16b-TT4.16b}, [x2], #64
258 sub w0, w0, #4
320 sub w0, w0, #1
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/linux/include/linux/mfd/
H A Drohm-bd957x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 * The BD9576 has own IRQ 'blocks' for:
18 * - I2C/thermal,
19 * - Over voltage protection
20 * - Short-circuit protection
21 * - Over current protection
22 * - Over voltage detection
23 * - Under voltage detection
24 * - Under voltage protection
25 * - 'system interrupt'.
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/linux/arch/x86/crypto/
H A Daes-ctr-avx-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
7 // This file is dual-licensed, meaning that you can use it under your choice of
13 // http://www.apache.org/licenses/LICENSE-2.0
45 //------------------------------------------------------------------------------
47 // This file contains x86_64 assembly implementations of AES-CTR and AES-XCTR
49 // - AES-NI && AVX
50 // - VAES && AVX2
51 // - VAES && AVX512BW && AVX512VL && BMI2
95 // Broadcast a 128-bit value from memory to all 128-bit lanes of a vector
119 sub $8, %ecx // LEN - 8
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H A Daes-gcm-aesni-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-NI optimized AES-GCM for x86_64
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
49 //------------------------------------------------------------------------------
51 // This file implements AES-GCM (Galois/Counter Mode) for x86_64 CPUs that
52 // support the original set of AES instructions, i.e. AES-NI. Two
55 // that the AVX implementation takes advantage of VEX-coded instructions in some
57 // implementation does *not* use 256-bit vectors, as AES is not supported on
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H A Daes-gcm-vaes-avx2.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-GCM implementation for x86_64 CPUs that support the following CPU
10 //------------------------------------------------------------------------------
12 // This file is dual-licensed, meaning that you can use it under your choice of
18 // http://www.apache.org/licenses/LICENSE-2.0
50 // -----------------------------------------------------------------------------
52 // This is similar to aes-gcm-vaes-avx512.S, but it uses AVX2 instead of AVX512.
73 // The below three 16-byte values must be in the order that they are, as
74 // they are really two 32-byte tables and a 16-byte value that overlap:
76 // - The first 32-byte table begins at .Lselect_high_bytes_table.
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H A Daes-xts-avx-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-XTS for modern x86_64 CPUs
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
50 * This file implements AES-XTS for modern x86_64 CPUs. To handle the
55 * AES-NI && AVX
56 * - 128-bit vectors (1 AES block per vector)
57 * - VEX-coded instructions
58 * - xmm0-xmm15
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H A Daes-gcm-vaes-avx512.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-GCM implementation for x86_64 CPUs that support the following CPU
10 //------------------------------------------------------------------------------
12 // This file is dual-licensed, meaning that you can use it under your choice of
18 // http://www.apache.org/licenses/LICENSE-2.0
55 // A shuffle mask that reflects the bytes of 16-byte blocks
63 // Alternatively, it can be interpreted as the naturally-ordered
73 // Values needed to prepare the initial vector of counter blocks.
80 // The number of AES blocks per vector, as a 128-bit value.
96 // This is immediately followed by three zeroized padding blocks, which are
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/linux/arch/arm/crypto/
H A Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
15 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
262 vld1.8 {\t0-\t1}, [bskey, :256]!
264 vld1.8 {\t2-\t3}, [bskey, :256]!
269 vld1.8 {\t0-\t1}, [bskey, :256]!
273 vld1.8 {\t2-\t3}, [bskey, :256]!
354 vld1.8 {\t0-\t1}, [bskey, :256]!
356 vld1.8 {\t2-\t3}, [bskey, :256]!
358 vld1.8 {\t4-\t5}, [bskey, :256]!
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H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
102 vld1.32 {q10-q11}, [ip]!
104 vld1.32 {q12-q13}, [ip]!
106 vld1.32 {q10-q11}, [ip]!
108 vld1.32 {q12-q13}, [ip]!
110 blo 0f @ AES-128: 10 rounds
111 vld1.32 {q10-q11}, [ip]!
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/linux/lib/zstd/compress/
H A Dzstd_compress_superblock.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
12 /*-*************************************
24 * Compresses literals section for a sub-block.
33 * hufMetadata->hType has literals block type info.
34 * If it is set_basic, all sub-blocks literals section will be Raw_Literals_Block.
35 * If it is set_rle, all sub-blocks literals section will be RLE_Literals_Block.
36 …* If it is set_compressed, first sub-block's literals section will be Compressed_Literals_Blo…
37 * If it is set_compressed, first sub-block's literals section will be Treeless_Literals_Block
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/linux/lib/crypto/x86/
H A Dsha256-ni-asm.S2 * Intel SHA Extensions optimized implementation of a SHA-256 update function
83 movdqa (\i-32)*4(SHA256CONSTANTS), MSG
100 * Intel SHA Extensions optimized implementation of a SHA-256 block function
102 * This function takes a pointer to the current SHA-256 state, a pointer to the
103 * input data, and the number of 64-byte blocks to process. Once all blocks
105 * only processes complete blocks. State initialization, buffering of partial
106 * blocks, and digest finalization is expected to be handled elsewhere.
120 * DCBA, HGFE -> ABEF, CDGH
223 // Do 4 rounds of SHA-256 for each of two messages (interleaved). m0_a and m0_b
228 // computes 4 more message schedule words for each message. m1_a-m3_a contain
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H A Dchacha-avx512vl-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ChaCha 256-bit cipher algorithm, x64 AVX-512VL functions
29 # %rsi: up to 2 data blocks output, o
30 # %rdx: up to 2 data blocks input, i
34 # This function encrypts two ChaCha blocks by loading the state
41 # x0..3[0-2] = s0..3
110 sub $2,%r8d
181 sub $1,%rax
194 # %rsi: up to 4 data blocks output, o
195 # %rdx: up to 4 data blocks input, i
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/linux/fs/xfs/scrub/
H A Drepair.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
58 * told us to fix it. This function returns -EAGAIN to mean "re-run scrub",
69 trace_xrep_attempt(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
71 xchk_ag_btcur_free(&sc->sa); in xrep_attempt()
72 xchk_rtgroup_btcur_free(&sc->sr); in xrep_attempt()
75 ASSERT(sc->ops->repair); in xrep_attempt()
76 run->repair_attempted = true; in xrep_attempt()
78 error = sc->ops->repair(sc); in xrep_attempt()
79 trace_xrep_done(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
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H A Dreap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2022-2023 Oracle. All Rights Reserved.
56 * Disposal of Blocks from Old Metadata
59 * to dispose of the blocks that (we think) the old btree was using.
62 * blocks with the same rmap owner that are owned by another data structure
64 * remaining in bitmap are the old btree's blocks.
67 * blocks on disk. The rmap data can tell us if there are multiple owners, so
74 * will be rebuilt (atop different blocks), thereby removing all the cross
103 * For AG blocks, this is reverse mapping owner and
110 /* For file blocks, this is the inode and fork. */
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/linux/arch/riscv/crypto/
H A Daes-riscv64-zvkned.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
41 // The generated code of this file depends on the following RISC-V extensions:
42 // - RV64I
43 // - RISC-V Vector ('V') with VLEN >= 128
44 // - RISC-V Vector AES block cipher extension ('Zvkned')
51 #include "aes-macros.S"
88 // t0 is the remaining length in 32-bit words. It's a multiple of 4.
91 sub t0, t0, t1 // Subtract number of words processed
134 addi LEN, LEN, -16
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H A Daes-riscv64-zvkned-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
50 #include "aes-macros.S"
63 // LEN32 = number of blocks, rounded up, in 32-bit words.
68 // Create a mask that selects the last 32-bit word of each 128-bit
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/linux/lib/crypto/arm64/
H A Dsha256-ce.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
51 * The SHA-256 round constants
75 ld1 { v0.4s- v3.4s}, [\tmp], #64
76 ld1 { v4.4s- v7.4s}, [\tmp], #64
77 ld1 { v8.4s-v11.4s}, [\tmp], #64
78 ld1 {v12.4s-v15.4s}, [\tmp]
94 0: ld1 {v16.4s-v19.4s}, [x1], #64
95 sub x2, x2, #1
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/linux/Documentation/devicetree/bindings/reset/
H A Dreset.txt8 Hardware blocks typically receive a reset signal. This signal is generated by
10 reset consumer (the module being reset, or a module managing when a sub-
15 specifier - a list of DT cells that represents the reset signal within the
21 in hardware for a reset signal to affect multiple logically separate HW blocks
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
41 rst: reset-controller {
42 #reset-cells = <1>;
51 #reset-cells, then only the phandle portion of the pair will
55 reset-names: List of reset signal name strings sorted in the same order as
56 the resets property. Consumers drivers will use reset-names to
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/linux/Documentation/filesystems/
H A Dzonefs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ZoneFS - Zone filesystem for Zoned block devices
11 as a file. Unlike a regular POSIX-compliant file system with native zoned block
18 than to a full-featured POSIX file system. The goal of zonefs is to simplify
22 example of this approach is the implementation of LSM (log-structured merge)
31 -------------------
62 by sub-directories. This file structure is built entirely using zone information
63 provided by the device and so does not require any complex on-disk metadata
66 On-disk metadata
67 ----------------
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/linux/Documentation/driver-api/media/
H A Dv4l2-intro.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------------
8 /dev, and create also non-V4L2 devices such as DVB, ALSA, FB, I2C and input
15 called 'sub-devices'.
22 connecting to sub-devices themselves. Some of this is quite complicated
28 So this framework sets up the basic building blocks that all drivers
32 A good example to look at as a reference is the v4l2-pci-skeleton.c
38 -------------------------
44 2) A way of initializing and commanding sub-devices (if any).
47 and keeping track of device-node specific data.
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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-c3-isp.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR MIT)
4 .. _v4l2-meta-fmt-c3isp-stats:
5 .. _v4l2-meta-fmt-c3isp-params:
17 Those statistics are obtained from the "c3-isp-stats" metadata capture video nodes,
21 The statistics collected are Auto-white balance,
22 Auto-exposure and Auto-focus information.
29 The configuration parameters are passed to the c3-isp-params metadata output video node,
31 sub-structs for each configurable area of the ISP, parameters for the C3-ISP
32 are defined as distinct structs or "blocks" which may be added to the data
34 populating the data member with the blocks that need to be configured by the driver, but
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/linux/drivers/gpu/drm/msm/
H A DNOTES4 display controller blocks at play:
5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
27 And one or more 'struct msm_gpu' for the various different gpu sub-
38 plane -> PIPE{RGBn,VGn} \
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