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Searched full:stval (Results 1 – 10 of 10) sorted by relevance

/linux/arch/riscv/kvm/
H A Dtrace.h38 __field(unsigned long, stval)
46 __entry->stval = trap->stval;
51 TP_printk("SEPC:0x%lx, SCAUSE:0x%lx, STVAL:0x%lx, HTVAL:0x%lx, HTINST:0x%lx",
54 __entry->stval,
H A Dvcpu_exit.c25 fault_addr = (trap->htval << 2) | (trap->stval & 0x3); in gstage_page_fault()
160 /* Update Guest SCAUSE, STVAL, and SEPC */ in kvm_riscv_vcpu_trap_redirect()
162 ncsr_write(CSR_VSTVAL, trap->stval); in kvm_riscv_vcpu_trap_redirect()
257 kvm_err("SCAUSE=0x%lx STVAL=0x%lx HTVAL=0x%lx HTINST=0x%lx\n", in kvm_riscv_vcpu_exit()
258 trap->scause, trap->stval, trap->htval, trap->htinst); in kvm_riscv_vcpu_exit()
H A Dvcpu_insn.c38 utrap.stval = insn; in truly_illegal_insn()
54 utrap.stval = insn; in truly_virtual_insn()
331 unsigned long insn = trap->stval; in kvm_riscv_vcpu_virtual_insn()
H A Dvcpu.c792 * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and in kvm_riscv_vcpu_enter_exit()
857 trap->stval = csr_read(CSR_STVAL); in kvm_riscv_vcpu_enter_exit()
/linux/arch/riscv/include/asm/
H A Dkgdb.h65 #define DBG_REG_BADADDR "stval"
H A Dkvm_host.h111 unsigned long stval; member
/linux/drivers/net/ethernet/amd/
H A Damd8111e.c402 writel(0, mmio + STVAL); in amd8111e_set_coalesce()
409 writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); /* 0.5 sec */ in amd8111e_set_coalesce()
540 /* Clear STVAL */ in amd8111e_init_hw_default()
541 writel(0x0, mmio + STVAL); in amd8111e_init_hw_default()
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c345 case KVM_REG_RISCV_CSR_REG(stval): in general_csr_id_to_str()
346 return RISCV_CSR_GENERAL(stval); in general_csr_id_to_str()
864 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval),
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml249 The standard Sstvala extension for stval provides all needed values
/linux/Documentation/virt/kvm/
H A Dapi.rst2848 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction