Searched +full:stm32mp25 +full:- +full:rifsc (Results 1 – 4 of 4) sorted by relevance
/freebsd/sys/contrib/device-tree/src/arm64/st/ |
H A D | stm32mp251.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 6 #include <dt-bindings/clock/st,stm32mp25-rcc.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/reset/st,stm32mp25-rcc.h> 9 #include <dt-bindings/regulator/st,stm32mp25-regulator.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 #address-cells = <1>; 17 #size-cells = <0>; [all …]
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H A D | stm32mp255.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 8 &rifsc { 10 compatible = "st,stm32mp25-vdec"; 14 access-controllers = <&rifsc 89>; 19 compatible = "st,stm32mp25-venc"; 23 access-controllers = <&rifsc 90>;
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H A D | stm32mp253.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 11 compatible = "arm,cortex-a35"; 14 enable-method = "psci"; 15 power-domains = <&CPU_PD1>; 16 power-domain-names = "psci"; 20 arm-pmu { 23 interrupt-affinity = <&cpu0>, <&cpu1>; 27 CPU_PD1: power-domain-cpu1 { 28 #power-domain-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | st,stm32mp25-rifsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gatien Chevallier <gatien.chevallier@foss.st.com> 17 The RIFSC (RIF security controller) is composed of three sets of registers, 19 - RISC registers associated with RISUP logic (resource isolation device unit 20 for peripherals), assign all non-RIF aware peripherals to zero, one or 22 - RIMC registers: associated with RIMU logic (resource isolation master 23 unit), assign all non RIF-aware bus master to one security domain by [all …]
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