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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
35 const MCSubtargetInfo &STI, raw_ostream &O);
37 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI,
45 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
48 const MCSubtargetInfo &STI, raw_ostream &O);
51 const MCSubtargetInfo &STI, raw_ostream &O);
53 const MCSubtargetInfo &STI, raw_ostream &O);
56 const MCSubtargetInfo &STI, raw_ostream &O);
58 const MCSubtargetInfo &STI, raw_ostream &O);
[all …]
H A DARMTargetStreamer.cpp131 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { in getArchForCPU() argument
132 if (STI.getCPU() == "xscale") in getArchForCPU()
135 if (STI.hasFeature(ARM::HasV9_0aOps)) in getArchForCPU()
137 else if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
138 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
141 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
143 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
145 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
146 if (STI.hasFeature(ARM::FeatureMClass) && STI in getArchForCPU()
167 isV8M(const MCSubtargetInfo & STI) isV8M() argument
176 emitTargetAttributes(const MCSubtargetInfo & STI) emitTargetAttributes() argument
322 createARMObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI) createARMObjectTargetStreamer() argument
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H A DARMMCCodeEmitter.cpp64 bool isThumb(const MCSubtargetInfo &STI) const { in isThumb()
65 return STI.hasFeature(ARM::ModeThumb); in isThumb()
68 bool isThumb2(const MCSubtargetInfo &STI) const { in isThumb2()
69 return isThumb(STI) && STI.hasFeature(ARM::FeatureThumb2); in isThumb2()
72 bool isTargetMachO(const MCSubtargetInfo &STI) const { in isTargetMachO()
73 const Triple &TT = STI.getTargetTriple(); in isTargetMachO()
83 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const;
97 const MCSubtargetInfo &STI) cons
624 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,unsigned FixupKind,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchTargetOpValue() argument
[all...]
H A DARMInstPrinter.cpp89 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
135 printSBitModifierOperand(MI, 6, STI, O); in printInst()
136 printPredicateOperand(MI, 4, STI, O); in printInst()
157 printSBitModifierOperand(MI, 5, STI, O); in printInst()
158 printPredicateOperand(MI, 3, STI, O); in printInst()
183 printPredicateOperand(MI, 2, STI, O); in printInst()
187 printRegisterList(MI, 4, STI, O); in printInst()
197 printPredicateOperand(MI, 4, STI, O); in printInst()
212 printPredicateOperand(MI, 2, STI, O); in printInst()
216 printRegisterList(MI, 4, STI, O); in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O);
34 const MCSubtargetInfo &STI, raw_ostream &O) override;
40 const MCSubtargetInfo &STI, raw_ostream &O);
42 const MCSubtargetInfo &STI, raw_ostream &O);
47 const MCSubtargetInfo &STI, raw_ostream &O);
50 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
52 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
60 const MCSubtargetInfo &STI, raw_ostream &O);
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H A DAMDGPUInstPrinter.cpp44 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
46 printInstruction(MI, Address, STI, OS); in printInst()
51 const MCSubtargetInfo &STI, in printU4ImmOperand() argument
57 const MCSubtargetInfo &STI, in printU16ImmOperand() argument
71 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
90 const MCSubtargetInfo &STI, in printU32ImmOperand() argument
103 const MCSubtargetInfo &STI, in printOffset() argument
112 if (AMDGPU::isGFX12(STI) && IsVBuffer) in printOffset()
120 const MCSubtargetInfo &STI, in printFlatOffset() argument
129 AMDGPU::isGFX12(STI); in printFlatOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h31 const MCSubtargetInfo &STI, raw_ostream &O) override;
38 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI, raw_ostream &O);
43 const MCSubtargetInfo &STI,
52 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI,
56 bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
59 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
63 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
73 printPostIncOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printPostIncOperand() argument
99 printMemExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemExtend() argument
118 printUImm12Offset(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printUImm12Offset() argument
124 printAMIndexedWB(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAMIndexedWB() argument
[all...]
H A DAArch64MCCodeEmitter.cpp57 const MCSubtargetInfo &STI) const;
63 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const;
95 const MCSubtargetInfo &STI) const;
101 const MCSubtargetInfo &STI) const;
108 const MCSubtargetInfo &STI) const;
114 const MCSubtargetInfo &STI) cons
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYELFStreamer.cpp32 const MCSubtargetInfo &STI) in CSKYTargetELFStreamer() argument
35 const FeatureBitset &Features = STI.getFeatureBits(); in CSKYTargetELFStreamer()
178 void CSKYTargetELFStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { in emitTargetAttributes() argument
179 StringRef CPU = STI.getCPU(); in emitTargetAttributes()
195 if (STI.hasFeature(CSKY::HasE1)) in emitTargetAttributes()
198 if (STI.hasFeature(CSKY::HasE2)) in emitTargetAttributes()
201 if (STI.hasFeature(CSKY::Has2E3)) in emitTargetAttributes()
204 if (STI.hasFeature(CSKY::HasMP)) in emitTargetAttributes()
207 if (STI.hasFeature(CSKY::Has3E3r1)) in emitTargetAttributes()
210 if (STI.hasFeature(CSKY::Has3r1E3r2)) in emitTargetAttributes()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h35 bool isMicroMips(const MCSubtargetInfo &STI) const;
36 bool isMips32r6(const MCSubtargetInfo &STI) const;
49 const MCSubtargetInfo &STI) const override;
55 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
79 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) cons
[all...]
H A DMipsInstPrinter.cpp81 StringRef Annot, const MCSubtargetInfo &STI, in printInst()
93 printSaveRestore(MI, STI, O); in printInst()
98 printSaveRestore(MI, STI, O); in printInst()
103 printSaveRestore(MI, STI, O); in printInst()
108 printSaveRestore(MI, STI, O); in printInst()
114 if (!printAliasInstr(MI, Address, STI, O) && in printInst()
115 !printAlias(*MI, Address, STI, O)) in printInst()
116 printInstruction(MI, Address, STI, O); in printInst()
129 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand()
146 const MCSubtargetInfo &STI, in printJumpOperand()
80 printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O) printInst() argument
128 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
145 printJumpOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printJumpOperand() argument
159 printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBranchOperand() argument
179 printUImm(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printUImm() argument
194 printMemOperand(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemOperand() argument
224 printMemOperandEA(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemOperandEA() argument
247 printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch) printAlias() argument
259 printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo0,unsigned OpNo1,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch) printAlias() argument
271 printAlias(const MCInst & MI,uint64_t Address,const MCSubtargetInfo & STI,raw_ostream & OS) printAlias() argument
342 printSaveRestore(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O) printSaveRestore() argument
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H A DMipsMCCodeEmitter.cpp119 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { in isMicroMips()
120 return STI.hasFeature(Mips::FeatureMicroMips); in isMicroMips()
123 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { in isMips32r6()
124 return STI.hasFeature(Mips::FeatureMips32r6); in isMips32r6()
136 const MCSubtargetInfo &STI) const { in emitInstruction()
163 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
174 if (isMicroMips(STI)) { in encodeInstruction()
175 if (isMips32r6(STI)) { in encodeInstruction()
192 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
197 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); in encodeInstruction()
131 emitInstruction(uint64_t Val,unsigned Size,const MCSubtargetInfo & STI,raw_ostream & OS) const emitInstruction() argument
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H A DMipsInstPrinter.h84 const MCSubtargetInfo &STI, raw_ostream &O);
89 const MCSubtargetInfo &STI, raw_ostream &O) override;
92 const MCSubtargetInfo &STI, raw_ostream &OS);
95 const MCSubtargetInfo &STI, raw_ostream &O);
98 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
101 const MCSubtargetInfo &STI, raw_ostream &O);
103 const MCSubtargetInfo &STI, raw_ostream &O);
105 void printUImm(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
107 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
110 const MCSubtargetInfo &STI, raw_ostream &O);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp168 /// \returns True if \p STI is AMDHSA.
169 bool isHsaAbi(const MCSubtargetInfo &STI) { in isHsaAbi() argument
170 return STI.getTargetTriple().getOS() == Triple::AMDHSA; in isHsaAbi()
767 AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI) in AMDGPUTargetID() argument
768 : STI(STI), XnackSetting(TargetIDSetting::Any), in AMDGPUTargetID()
770 if (!STI.getFeatureBits().test(FeatureSupportsXNACK)) in AMDGPUTargetID()
772 if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC)) in AMDGPUTargetID()
860 auto TargetTriple = STI.getTargetTriple(); in toString()
861 auto Version = getIsaVersion(STI.getCPU()); in toString()
873 Processor = STI.getCPU().str(); in toString()
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H A DAMDGPUBaseInfo.h57 /// \returns True if \p STI is AMDHSA.
58 bool isHsaAbi(const MCSubtargetInfo &STI);
125 const MCSubtargetInfo &STI;
130 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
198 /// \returns Wavefront size for given subtarget \p STI.
199 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
201 /// \returns Local memory size in bytes for given subtarget \p STI.
202 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
205 /// \p STI.
206 unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI);
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.h36 const MCSubtargetInfo &STI, raw_ostream &O) override;
41 const MCSubtargetInfo &STI, raw_ostream &O);
45 const MCSubtargetInfo &STI, raw_ostream &OS);
48 const MCSubtargetInfo &STI, raw_ostream &OS);
50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
53 const MCSubtargetInfo &STI, raw_ostream &O,
56 const MCSubtargetInfo &STI, raw_ostream &O);
59 const MCSubtargetInfo &STI, raw_ostream &O);
61 const MCSubtargetInfo &STI, raw_ostream &O);
63 const MCSubtargetInfo &STI, raw_ostream &O);
[all …]
H A DPPCMCCodeEmitter.h40 const MCSubtargetInfo &STI) const;
43 const MCSubtargetInfo &STI) const;
46 const MCSubtargetInfo &STI) const;
49 const MCSubtargetInfo &STI) const;
52 const MCSubtargetInfo &STI) const;
55 const MCSubtargetInfo &STI,
59 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) cons
[all...]
H A DPPCInstPrinter.cpp56 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
74 printOperand(MI, 0, STI, O); in printInst()
76 printOperand(MI, 2, STI, O); in printInst()
78 printOperand(MI, 1, STI, O); in printInst()
97 printInstruction(MI, Address, STI, O); in printInst()
127 printOperand(MI, 0, STI, O); in printInst()
129 printOperand(MI, 1, STI, O); in printInst()
144 printOperand(MI, 0, STI, O); in printInst()
146 printOperand(MI, 1, STI, O); in printInst()
164 (!TT.isOSAIX() || STI in printInst()
219 printPredicateOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O,const char * Modifier) printPredicateOperand() argument
317 printATBitsAsHint(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printATBitsAsHint() argument
327 printU1ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU1ImmOperand() argument
335 printU2ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU2ImmOperand() argument
343 printU3ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU3ImmOperand() argument
351 printU4ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU4ImmOperand() argument
359 printS5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS5ImmOperand() argument
367 printImmZeroOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printImmZeroOperand() argument
375 printU5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU5ImmOperand() argument
383 printU6ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU6ImmOperand() argument
391 printU7ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU7ImmOperand() argument
402 printU8ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU8ImmOperand() argument
409 printU10ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU10ImmOperand() argument
417 printU12ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU12ImmOperand() argument
425 printS16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS16ImmOperand() argument
434 printS34ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS34ImmOperand() argument
446 printU16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU16ImmOperand() argument
456 printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBranchOperand() argument
482 printAbsBranchOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printAbsBranchOperand() argument
491 printcrbitm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printcrbitm() argument
509 printMemRegImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm() argument
521 printMemRegImmHash(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImmHash() argument
530 printMemRegImm34PCRel(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34PCRel() argument
539 printMemRegImm34(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34() argument
548 printMemRegReg(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegReg() argument
562 printTLSCall(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printTLSCall() argument
644 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
[all...]
H A DPPCMCCodeEmitter.cpp46 const MCSubtargetInfo &STI) const { in getDirectBrEncoding()
50 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
156 const MCSubtargetInfo &STI) const { in getDispRIEncoding()
158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIEncoding()
169 const MCSubtargetInfo &STI) const { in getDispRIXEncoding()
171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIXEncoding()
182 const MCSubtargetInfo &STI) const { in getDispRIX16Encoding()
184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIX16Encoding()
195 const MCSubtargetInfo &STI) const { in getDispRIHashEncoding()
197 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getDispRIHashEncoding()
122 getImm34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,MCFixupKind Fixup) const getImm34Encoding() argument
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
21 - sti-display-subsystem: Master device for DRM sub-components
25 - compatible: "st,sti-display-subsystem"
28 - sti-compositor: frame compositor engine
29 must be a child of sti-display-subsystem
44 - sti-tvout: video out hardware block
45 must be a child of sti-display-subsystem
56 - sti-hdmi: hdmi output block
57 must be a child of sti-display-subsystem
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.h30 const MCSubtargetInfo &STI, raw_ostream &O) override;
33 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI, raw_ostream &O);
38 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI, raw_ostream &O);
41 void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
44 const MCSubtargetInfo &STI, raw_ostream &O);
46 const MCSubtargetInfo &STI, raw_ostream &O);
48 const MCSubtargetInfo &STI, raw_ostream &O);
49 void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
[all …]
H A DRISCVMCCodeEmitter.cpp54 const MCSubtargetInfo &STI) const override;
58 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
66 const MCSubtargetInfo &STI) const;
70 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) const;
90 const MCSubtargetInfo &STI) const;
94 const MCSubtargetInfo &STI) const;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp52 const MCSubtargetInfo &STI);
54 const MCSubtargetInfo &STI);
56 const MCSubtargetInfo &STI);
86 const MCSubtargetInfo &STI) { in emitSIC() argument
90 OutStreamer.emitInstruction(SICInst, STI); in emitSIC()
94 const MCSubtargetInfo &STI) { in emitBSIC() argument
102 OutStreamer.emitInstruction(BSICInst, STI); in emitBSIC()
106 const MCSubtargetInfo &STI) { in emitLEAzzi() argument
114 OutStreamer.emitInstruction(LEAInst, STI); in emitLEAzzi()
118 const MCSubtargetInfo &STI) { in emitLEASLzzi() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp40 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
42 if (!printAliasInstr(MI, Address, STI, OS)) in printInst()
43 printInstruction(MI, Address, STI, OS); in printInst()
48 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand() argument
68 const MCSubtargetInfo &STI, in printMemASXOperand() argument
72 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
74 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
82 printOperand(MI, OpNum + 2, STI, O); in printMemASXOperand()
99 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
105 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaMCCodeEmitter.cpp48 const MCSubtargetInfo &STI) const override;
54 const MCSubtargetInfo &STI) const;
60 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
[all …]

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