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/linux/arch/mips/bcm63xx/
H A Dclk.c28 static DEFINE_MUTEX(clocks_mutex);
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked()
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument
48 if (enable) in bcm_hwclock_set()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
[all …]
/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
29 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
30 #define USBHEN_E (1 << 2) /* OHCI block enable */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
35 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
40 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
41 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
42 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
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/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
30 #define CKENA (0x000C) /* A Clock Enable Register */
31 #define CKENB (0x0010) /* B Clock Enable Register */
32 #define CKENC (0x0024) /* C Clock Enable Register */
38 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
[all …]
/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
34 static const struct iproc_pll_ctrl sr_genpll0 = {
47 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
57 .enable = ENABLE_VAL(0x4, 7, 1, 13),
63 .enable = ENABLE_VAL(0x4, 8, 2, 14),
69 .enable = ENABLE_VAL(0x4, 9, 3, 15),
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H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
31 static const struct iproc_pll_ctrl genpll_scr = {
43 static const struct iproc_clk_ctrl genpll_scr_clk[] = {
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
57 .enable = ENABLE_VAL(0x0, 19, 13, 0),
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
69 .enable = ENABLE_VAL(0x0, 21, 15, 0),
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
41 static void __init cygnus_armpll_init(struct device_node *node) in cygnus_armpll_init()
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
47 static const struct iproc_pll_ctrl genpll = {
61 static const struct iproc_clk_ctrl genpll_clk[] = {
65 .enable = ENABLE_VAL(0x4, 6, 0, 12),
71 .enable = ENABLE_VAL(0x4, 7, 1, 13),
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/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
129 static inline void vpif_set_bit(u32 reg, u32 bit) in vpif_set_bit()
134 static inline void vpif_clr_bit(u32 reg, u32 bit) in vpif_clr_bit()
145 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
183 /* bit position of clock and channel enable in vpif_chn_ctrl register */
262 /* inline function to enable/disable channel0 */
263 static inline void enable_channel0(int enable) in enable_channel0() argument
265 if (enable) in enable_channel0()
271 /* inline function to enable/disable channel1 */
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/linux/sound/soc/codecs/
H A Dab8500-codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
8 * for ST-Ericsson.
14 * for ST-Ericsson.
29 #include <linux/mfd/abx500/ab8500-sysctrl.h>
30 #include <linux/mfd/abx500/ab8500-codec.h>
39 #include <sound/soc-dapm.h>
42 #include "ab8500-codec.h"
56 /* Nr of FIR/IIR-coeff banks in ANC-block */
77 static const char * const enum_sid_state[] = {
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H A Dmt6357.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
17 static void set_playback_gpio(struct mt6357_priv *priv, bool enable) in set_playback_gpio() argument
19 regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, MT6357_GPIO_MODE2_CLEAR_ALL); in set_playback_gpio()
20 if (enable) { in set_playback_gpio()
22 regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, in set_playback_gpio()
32 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0, in set_playback_gpio()
44 static void set_capture_gpio(struct mt6357_priv *priv, bool enable) in set_capture_gpio() argument
46 regmap_write(priv->regmap, MT6357_GPIO_MODE3_CLR, MT6357_GPIO_MODE3_CLEAR_ALL); in set_capture_gpio()
47 if (enable) { in set_capture_gpio()
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H A Dcs530x.c1 // SPDX-License-Identifier: GPL-2.0
27 static const char *cs530x_supply_names[CS530X_NUM_SUPPLIES] = {
28 "vdd-a",
29 "vdd-io",
32 static const struct reg_default cs530x_reg_defaults[] = {
55 static bool cs530x_read_and_write_regs(unsigned int reg) in cs530x_read_and_write_regs()
84 static bool cs530x_readable_register(struct device *dev, unsigned int reg) in cs530x_readable_register()
95 static bool cs530x_writeable_register(struct device *dev, unsigned int reg) in cs530x_writeable_register()
106 static int cs530x_put_volsw_vu(struct snd_kcontrol *kcontrol, in cs530x_put_volsw_vu()
112 struct regmap *regmap = cs530x->regmap; in cs530x_put_volsw_vu()
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H A Dnau8315.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8315.c -- NAU8315 ALSA SoC Audio Amplifier Driver
22 #include <sound/soc-dai.h>
23 #include <sound/soc-dapm.h>
26 struct gpio_desc *enable; member
30 static int nau8315_daiops_trigger(struct snd_pcm_substream *substream, in nau8315_daiops_trigger()
33 struct snd_soc_component *component = dai->component; in nau8315_daiops_trigger()
37 if (!nau8315->enable) in nau8315_daiops_trigger()
44 if (nau8315->enpin_switch) { in nau8315_daiops_trigger()
45 gpiod_set_value(nau8315->enable, 1); in nau8315_daiops_trigger()
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H A Dmt6358.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
107 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
112 static void playback_gpio_set(struct mt6358_priv *priv) in playback_gpio_set()
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
123 static void playback_gpio_reset(struct mt6358_priv *priv) in playback_gpio_reset()
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
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H A Dwcd-clsh-v2.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
10 #include "wcd-clsh-v2.h"
22 /* Class-H registers for codecs from and above WCD9335 */
119 static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl, in wcd_enable_clsh_block()
120 bool enable) in wcd_enable_clsh_block() argument
122 struct snd_soc_component *comp = ctrl->comp; in wcd_enable_clsh_block()
124 if ((enable && ++ctrl->clsh_users == 1) || in wcd_enable_clsh_block()
125 (!enable && --ctrl->clsh_users == 0)) in wcd_enable_clsh_block()
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H A Dak4535.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ak4535.c -- AK4535 ALSA Soc Audio driver
37 static const struct reg_default ak4535_reg_defaults[] = {
55 static bool ak4535_volatile(struct device *dev, unsigned int reg) in ak4535_volatile()
65 static const char *ak4535_mono_gain[] = {"+6dB", "-17dB"};
66 static const char *ak4535_mono_out[] = {"(L + R)/2", "Hi-Z"};
67 static const char *ak4535_hp_out[] = {"Stereo", "Mono"};
68 static const char *ak4535_deemp[] = {"44.1kHz", "Off", "48kHz", "32kHz"};
69 static const char *ak4535_mic_select[] = {"Internal", "External"};
71 static const struct soc_enum ak4535_enum[] = {
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/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-gpio.c -- Mediatek 8192 afe gpio ctrl
11 #include "mt8192-afe-common.h"
12 #include "mt8192-afe-gpio.h"
14 static struct pinctrl *aud_pinctrl;
60 static struct audio_gpio_attr aud_gpios[MT8192_AFE_GPIO_GPIO_NUM] = {
101 static DEFINE_MUTEX(gpio_request_mutex);
103 static int mt8192_afe_gpio_select(struct device *dev, in mt8192_afe_gpio_select()
111 return -EINVAL; in mt8192_afe_gpio_select()
117 return -EIO; in mt8192_afe_gpio_select()
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/linux/drivers/acpi/
H A Dosi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * osi.c - _OSI implementation
27 bool enable; member
30 static struct acpi_osi_config {
40 static struct acpi_osi_config osi_config;
41 static struct acpi_osi_entry
49 static u32 acpi_osi_handler(acpi_string interface, u32 supported) in acpi_osi_handler()
72 bool enable = true; in acpi_osi_setup() local
96 osi->enable = false; in acpi_osi_setup()
103 enable = false; in acpi_osi_setup()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dih_v6_0.c37 static void ih_v6_0_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
46 static void ih_v6_0_init_register_offset(struct amdgpu_device *adev) in ih_v6_0_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
[all …]
H A Dih_v7_0.c37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings
46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev) in ih_v7_0_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v7_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v7_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v7_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v7_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v7_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v7_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v7_0_init_register_offset()
[all …]
H A Dih_v6_1.c37 static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
46 static void ih_v6_1_init_register_offset(struct amdgpu_device *adev) in ih_v6_1_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
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H A Dnavi10_ih.c40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
43 * navi10_ih_init_register_offset - Initialize register offset for ih rings
49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) in navi10_ih_init_register_offset()
53 if (adev->irq.ih.ring_size) { in navi10_ih_init_register_offset()
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fifo_underrun.c58 static bool ivb_can_enable_err_int(struct drm_device *dev) in ivb_can_enable_err_int()
65 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
70 if (crtc->cpu_fifo_underrun_disabled) in ivb_can_enable_err_int()
77 static bool cpt_can_enable_serr_int(struct drm_device *dev) in cpt_can_enable_serr_int()
84 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
89 if (crtc->pch_fifo_underrun_disabled) in cpt_can_enable_serr_int()
96 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) in i9xx_check_fifo_underruns()
99 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns()
100 i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
103 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
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/linux/drivers/clk/meson/
H A Dvclk.c1 // SPDX-License-Identifier: GPL-2.0
11 static inline struct meson_vclk_gate_data *
14 return (struct meson_vclk_gate_data *)clk->data; in clk_get_meson_vclk_gate_data()
17 static int meson_vclk_gate_enable(struct clk_hw *hw) in meson_vclk_gate_enable()
22 meson_parm_write(clk->map, &vclk->enable, 1); in meson_vclk_gate_enable()
25 meson_parm_write(clk->map, &vclk->reset, 1); in meson_vclk_gate_enable()
26 meson_parm_write(clk->map, &vclk->reset, 0); in meson_vclk_gate_enable()
31 static void meson_vclk_gate_disable(struct clk_hw *hw) in meson_vclk_gate_disable()
36 meson_parm_write(clk->map, &vclk->enable, 0); in meson_vclk_gate_disable()
39 static int meson_vclk_gate_is_enabled(struct clk_hw *hw) in meson_vclk_gate_is_enabled()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_policy.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
21 static int guc_action_update_vgt_policy(struct xe_guc *guc, u64 addr, u32 size) in guc_action_update_vgt_policy()
30 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_update_vgt_policy()
37 static int pf_send_policy_klvs(struct xe_gt *gt, const u32 *klvs, u32 num_dwords) in pf_send_policy_klvs()
42 struct xe_guc *guc = &gt->uc.guc; in pf_send_policy_klvs()
54 xe_map_memcpy_to(xe, &bo->vmap, 0, klvs, bytes); in pf_send_policy_klvs()
64 * Return: 0 on success, -ENOKEY if some KLVs were not updated, -EPROTO if reply was malformed,
67 static int pf_push_policy_klvs(struct xe_gt *gt, u32 num_klvs, in pf_push_policy_klvs()
77 int err = ret < 0 ? ret : ret < num_klvs ? -ENOKEY : -EPROTO; in pf_push_policy_klvs()
[all …]
/linux/drivers/fpga/tests/
H A Dfpga-bridge-test.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/fpga/fpga-bridge.h>
17 bool enable; member
33 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
35 struct bridge_stats *stats = bridge->priv; in op_enable_set()
37 stats->enable = enable; in op_enable_set()
46 static const struct fpga_bridge_ops fake_bridge_ops = {
51 * register_test_bridge() - Register a fake FPGA bridge for testing.
57 static struct bridge_ctx *register_test_bridge(struct kunit *test, const char *dev_name) in register_test_bridge()
65 ctx->dev = kunit_device_register(test, dev_name); in register_test_bridge()
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_mitigations.c1 // SPDX-License-Identifier: MIT
15 static unsigned long mitigations __read_mostly = ~0UL;
21 static const char * const names[] = {
30 static int mitigations_set(const char *val, const struct kernel_param *kp) in mitigations_set()
41 return -ENOMEM; in mitigations_set()
44 bool enable = true; in mitigations_set() local
62 enable = !enable; in mitigations_set()
67 enable = !enable; in mitigations_set()
76 if (enable) in mitigations_set()
86 err = -EINVAL; in mitigations_set()
[all …]

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