Home
last modified time | relevance | path

Searched +full:static +full:- +full:enable (Results 1 – 25 of 1081) sorted by relevance

12345678910>>...44

/linux/arch/mips/bcm63xx/
H A Dclk.c28 static DEFINE_MUTEX(clocks_mutex);
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked()
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument
48 if (enable) in bcm_hwclock_set()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
[all …]
/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
29 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
30 #define USBHEN_E (1 << 2) /* OHCI block enable */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
35 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
40 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
41 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
42 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
[all …]
/linux/sound/soc/codecs/
H A Dcs530x.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2024-2025 Cirrus Logic, Inc. and
25 static const char *cs530x_supply_names[CS530X_NUM_SUPPLIES] = {
26 "vdd-a",
27 "vdd-io",
30 static const struct reg_default cs530x_reg_defaults[] = {
65 static bool cs530x_read_and_write_regs(unsigned int reg) in cs530x_read_and_write_regs()
107 static bool cs530x_readable_register(struct device *dev, unsigned int reg) in cs530x_readable_register()
118 static bool cs530x_writeable_register(struct device *dev, unsigned int reg) in cs530x_writeable_register()
130 static int cs530x_put_volsw_vu(struct snd_kcontrol *kcontrol, in cs530x_put_volsw_vu()
[all …]
H A Dmt6357.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
17 static void set_playback_gpio(struct mt6357_priv *priv, bool enable) in set_playback_gpio() argument
19 regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, MT6357_GPIO_MODE2_CLEAR_ALL); in set_playback_gpio()
20 if (enable) { in set_playback_gpio()
22 regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, in set_playback_gpio()
32 regmap_update_bits(priv->regma in set_playback_gpio()
44 set_capture_gpio(struct mt6357_priv * priv,bool enable) set_capture_gpio() argument
104 hp_pull_down(struct mt6357_priv * priv,bool enable) hp_pull_down() argument
318 mt6357_set_dmic(struct mt6357_priv * priv,bool enable) mt6357_set_dmic() argument
368 mt6357_set_amic(struct mt6357_priv * priv,bool enable,unsigned int mic_type) mt6357_set_amic() argument
462 mt6357_set_loopback(struct mt6357_priv * priv,bool enable) mt6357_set_loopback() argument
503 mt6357_set_ul_sine_gen(struct mt6357_priv * priv,bool enable) mt6357_set_ul_sine_gen() argument
793 configure_downlinks(struct mt6357_priv * priv,bool enable) configure_downlinks() argument
[all...]
H A Dab8500-codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
8 * for ST-Ericsson.
14 * for ST-Ericsson.
27 #include <linux/mfd/abx500/ab8500-sysctrl.h>
28 #include <linux/mfd/abx500/ab8500-codec.h>
37 #include <sound/soc-dapm.h>
40 #include "ab8500-codec.h"
54 /* Private data for AB8500 device-driver */
59 static inline const char *amic_micbias_str(enum amic_micbias micbias) in amic_micbias_str()
[all …]
H A Drt9123p.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt9123p.c -- RT9123 (HW Mode) ALSA SoC Codec driver
18 #include <sound/soc-dai.h>
19 #include <sound/soc-dapm.h>
22 struct gpio_desc *enable; member
27 static int rt9123p_daiops_trigger(struct snd_pcm_substream *substream, int cmd, in rt9123p_daiops_trigger()
30 struct snd_soc_component *comp = dai->component; in rt9123p_daiops_trigger()
33 if (!rt9123p->enable) in rt9123p_daiops_trigger()
40 mdelay(rt9123p->enable_delay); in rt9123p_daiops_trigger()
41 if (rt9123p->enable_switch) { in rt9123p_daiops_trigger()
[all …]
H A Dnau8315.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8315.c -- NAU8315 ALSA SoC Audio Amplifier Driver
21 #include <sound/soc-dai.h>
22 #include <sound/soc-dapm.h>
25 struct gpio_desc *enable;
29 static in
26 struct gpio_desc *enable; global() member
[all...]
H A Dak4535.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ak4535.c -- AK4535 ALSA Soc Audio driver
37 static const struct reg_default ak4535_reg_defaults[] = {
55 static bool ak4535_volatile(struct device *dev, unsigned int reg) in ak4535_volatile()
65 static const char *ak4535_mono_gain[] = {"+6dB", "-1
[all...]
H A Dwcd-clsh-v2.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
10 #include "wcd-clsh-v2.h"
22 /* Class-H registers for codecs from and above WCD9335 */
119 static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl, in wcd_enable_clsh_block()
120 bool enable) in wcd_enable_clsh_block() argument
177 wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl * ctrl,int mode,bool enable) wcd_clsh_buck_ctrl() argument
197 wcd_clsh_v3_buck_ctrl(struct snd_soc_component * component,struct wcd_clsh_ctrl * ctrl,int mode,bool enable) wcd_clsh_v3_buck_ctrl() argument
226 wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl * ctrl,int mode,bool enable) wcd_clsh_flyback_ctrl() argument
414 wcd_clsh_v3_force_iq_ctl(struct snd_soc_component * component,int mode,bool enable) wcd_clsh_v3_force_iq_ctl() argument
455 wcd_clsh_v3_flyback_ctrl(struct snd_soc_component * component,struct wcd_clsh_ctrl * ctrl,int mode,bool enable) wcd_clsh_v3_flyback_ctrl() argument
[all...]
H A Drt9123.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt9123.c -- RT9123 (SW I2C Mode) ALSA SoC Codec driver
24 #include <sound/soc-dai.h>
25 #include <sound/soc-dapm.h>
47 struct gpio_desc *enable; member
53 static int rt9123_enable_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, in rt9123_enable_event()
56 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); in rt9123_enable_event()
57 struct device *dev = comp->dev; in rt9123_enable_event()
58 unsigned int enable; in rt9123_enable_event() local
63 enable = 1; in rt9123_enable_event()
[all …]
H A Dmt6358.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
106 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
111 static void playback_gpio_set(struct mt6358_priv *priv) in playback_gpio_set()
114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
116 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
118 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
122 static void playback_gpio_reset(struct mt6358_priv *priv) in playback_gpio_reset()
129 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
131 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
[all …]
/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
30 #define CKENA (0x000C) /* A Clock Enable Register */
31 #define CKENB (0x0010) /* B Clock Enable Register */
32 #define CKENC (0x0024) /* C Clock Enable Register */
38 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
[all …]
/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
34 static const struct iproc_pll_ctrl sr_genpll0 = {
47 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
57 .enable = ENABLE_VAL(0x4, 7, 1, 13),
63 .enable = ENABLE_VAL(0x4, 8, 2, 14),
69 .enable = ENABLE_VAL(0x4, 9, 3, 15),
[all …]
H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
31 static const struct iproc_pll_ctrl genpll_scr = {
43 static const struct iproc_clk_ctrl genpll_scr_clk[] = {
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
57 .enable = ENABLE_VAL(0x0, 19, 13, 0),
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
69 .enable = ENABLE_VAL(0x0, 21, 15, 0),
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
41 static void __init cygnus_armpll_init(struct device_node *node) in cygnus_armpll_init()
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
47 static const struct iproc_pll_ctrl genpll = {
61 static const struct iproc_clk_ctrl genpll_clk[] = {
65 .enable = ENABLE_VAL(0x4, 6, 0, 12),
71 .enable = ENABLE_VAL(0x4, 7, 1, 13),
[all …]
/linux/drivers/power/sequencing/
H A Dpwrseq-qcom-wcn.c1 // SPDX-License-Identifier: GPL-2.0-only
43 static void pwrseq_qcom_wcn_ensure_gpio_delay(struct pwrseq_qcom_wcn_ctx *ctx) in pwrseq_qcom_wcn_ensure_gpio_delay()
48 if (!ctx->pdata->gpio_enable_delay_ms) in pwrseq_qcom_wcn_ensure_gpio_delay()
51 diff_jiffies = jiffies - ctx->last_gpio_enable_jf; in pwrseq_qcom_wcn_ensure_gpio_delay()
54 if (diff_msecs < ctx->pdata->gpio_enable_delay_ms) in pwrseq_qcom_wcn_ensure_gpio_delay()
55 msleep(ctx->pdata->gpio_enable_delay_ms - diff_msecs); in pwrseq_qcom_wcn_ensure_gpio_delay()
58 static int pwrseq_qcom_wcn_vddio_enable(struct pwrseq_device *pwrseq) in pwrseq_qcom_wcn_vddio_enable()
62 return regulator_enable(ctx->vddio); in pwrseq_qcom_wcn_vddio_enable()
65 static int pwrseq_qcom_wcn_vddio_disable(struct pwrseq_device *pwrseq) in pwrseq_qcom_wcn_vddio_disable()
69 return regulator_disable(ctx->vddio); in pwrseq_qcom_wcn_vddio_disable()
[all …]
/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
129 static inline void vpif_set_bit(u32 reg, u32 bit) in vpif_set_bit()
134 static inline void vpif_clr_bit(u32 reg, u32 bit) in vpif_clr_bit()
145 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
183 /* bit position of clock and channel enable in vpif_chn_ctrl register */
262 /* inline function to enable/disable channel0 */
263 static inline void enable_channel0(int enable) in enable_channel0() argument
265 if (enable) in enable_channel0()
271 /* inline function to enable/disable channel1 */
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-gpio.c -- Mediatek 8192 afe gpio ctrl
11 #include "mt8192-afe-common.h"
12 #include "mt8192-af
164 mt8192_afe_gpio_adda_dl(struct device * dev,bool enable) mt8192_afe_gpio_adda_dl() argument
175 mt8192_afe_gpio_adda_ul(struct device * dev,bool enable) mt8192_afe_gpio_adda_ul() argument
186 mt8192_afe_gpio_adda_ch34_dl(struct device * dev,bool enable) mt8192_afe_gpio_adda_ch34_dl() argument
197 mt8192_afe_gpio_adda_ch34_ul(struct device * dev,bool enable) mt8192_afe_gpio_adda_ch34_ul() argument
208 mt8192_afe_gpio_request(struct device * dev,bool enable,int dai,int uplink) mt8192_afe_gpio_request() argument
[all...]
/linux/drivers/acpi/
H A Dosi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * osi.c - _OSI implementation
27 bool enable; member
30 static struct acpi_osi_config {
40 static struct acpi_osi_config osi_config;
41 static struct acpi_osi_entry
48 static u32 acpi_osi_handler(acpi_string interface, u32 supported) in acpi_osi_handler()
71 bool enable = true; in acpi_osi_setup() local
95 osi->enable = false; in acpi_osi_setup()
102 enable = false; in acpi_osi_setup()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dih_v6_1.c37 static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
46 static void ih_v6_1_init_register_offset(struct amdgpu_device *adev) in ih_v6_1_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
[all …]
/linux/drivers/fpga/tests/
H A Dfpga-bridge-test.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/fpga/fpga-bridge.h>
17 bool enable; member
33 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
35 struct bridge_stats *stats = bridge->priv; in op_enable_set()
37 stats->enable = enable; in op_enable_set()
46 static const struct fpga_bridge_ops fake_bridge_ops = {
51 * register_test_bridge() - Register a fake FPGA bridge for testing.
57 static struct bridge_ctx *register_test_bridge(struct kunit *test, const char *dev_name) in register_test_bridge()
65 ctx->dev = kunit_device_register(test, dev_name); in register_test_bridge()
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_mitigations.c1 // SPDX-License-Identifier: MIT
15 static unsigned long mitigations __read_mostly = ~0UL;
21 static const char * const names[] = {
30 static int mitigations_set(const char *val, const struct kernel_param *kp) in mitigations_set()
41 return -ENOMEM; in mitigations_set()
44 bool enable = true; in mitigations_set() local
62 enable = !enable; in mitigations_set()
67 enable = !enable; in mitigations_set()
76 if (enable) in mitigations_set()
86 err = -EINVAL; in mitigations_set()
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-ctcu-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
19 #include "coresight-ctcu.h"
20 #include "coresight-priv.h"
22 #define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
23 #define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
28 * ATID register is 32 bits. Therefore, an ETR device has a 128-bit long field
32 * ------------------------------------------------------
34 * ------------------------------------------------------
38 * -------------------------
[all …]
/linux/drivers/rtc/
H A Drtc-ab-b5ze-s3.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
10 * https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
12 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
24 #define DRV_NAME "rtc-ab-b5ze-s3"
28 #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
29 #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
30 #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
33 #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
37 #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
[all …]
/linux/drivers/watchdog/
H A Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
35 * [0]: reset enable;
36 * [1]: interrupt enable && watchdog enable
66 static bool nowayout = WATCHDOG_NOWAYOUT;
67 static int heartbeat;
68 static bool early_enable = STARFIVE_WDT_EARLY_ENA;
83 unsigned int control; /* Watchdog Control Register for reset enable */
86 unsigned int enable; /* Watchdog Enable Register */ member
113 static const struct starfive_wdt_variant starfive_wdt_jh7100_variant = {
117 .enable = STARFIVE_WDT_JH7100_EN,
[all …]

12345678910>>...44