/freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
H A D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h> 12 compatible = "starfive,jh7100"; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; 18 #size-cells = <0>; [all …]
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H A D | jh7100-beaglev-starlight.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 7 /dts-v1/; 8 #include "jh7100-common.dtsi" 12 compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; 16 phy-handle = <&phy>; 20 phy: ethernet-phy@7 { 22 reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
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H A D | jh7100-starfive-visionfive-v1.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 7 /dts-v1/; 8 #include "jh7100-common.dtsi" 11 model = "StarFive VisionFive V1"; 12 compatible = "starfive,visionfive-v1", "starfive,jh7100"; 14 gpio-restart { 15 compatible = "gpio-restart"; 22 phy-handle = <&phy>; 26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires [all …]
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H A D | jh7100-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 7 /dts-v1/; 8 #include "jh7100.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> 21 stdout-path = "serial0:115200n8"; 25 timebase-frequency = <6250000>; 34 compatible = "gpio-leds"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
H A D | starfive,jh7100-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive Watchdog for JH7100 and JH7110 SoC 10 - Xingyu Wu <xingyu.wu@starfivetech.com> 11 - Samin Guo <samin.guo@starfivetech.com> 14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog 25 - enum: 26 - starfive,jh7100-wdt [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | starfive,jh7100-audclk.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive JH7100 Audio Clock Generator 10 - Emil Renner Berthing <kernel@esmil.dk> 14 const: starfive,jh7100-audclk 21 - description: Audio source clock 22 - description: External 12.288MHz clock 23 - description: Domain 7 AHB bus clock [all …]
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H A D | starfive,jh7100-clkgen.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive JH7100 Clock Generator 10 - Geert Uytterhoeven <geert@linux-m68k.org> 11 - Emil Renner Berthing <kernel@esmil.dk> 15 const: starfive,jh7100-clkgen 22 - description: Main clock source (25 MHz) 23 - description: Application-specific clock source (12-27 MHz) [all …]
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
H A D | starfive,jh71x0-temp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/hwmon/starfive,jh71x [all...] |
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | starfive,jh7100-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive JH7100 Pin Controller 10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd. 15 interesting 2-layered approach to pin muxing best illustrated by the diagram 21 LCD output -----------------| | 22 CMOS Camera interface ------| |--- PAD_GPIO[0] 23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1] [all …]
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/freebsd/sys/contrib/device-tree/Bindings/reset/ |
H A D | starfive,jh7100-reset.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive JH7100 SoC Reset Controller 10 - Emil Renner Berthing <kernel@esmil.dk> 15 - starfive,jh7100-reset 20 "#reset-cells": 24 - compatible 25 - reg [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2022 StarFive Technology Co., Ltd. 4 --- 5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: StarFive JH7110 DWMAC glue layer 11 - Emil Renner Berthing <kernel@esmil.dk> 12 - Samin Guo <samin.guo@starfivetech.com> 19 - starfive,jh7100-dwmac 20 - starfive,jh7110-dwmac [all …]
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H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 - Giuseppe Cavallaro <peppe.cavallaro@st.com> 12 - Jose Abreu <joabreu@synopsys.com> 23 - snps,dwmac 24 - snps,dwmac-3.40a 25 - snps,dwmac-3.50a 26 - snps,dwmac-3.610 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/riscv/ |
H A D | starfive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/riscv/starfive.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive SoC-based boards 10 - Michael Zhu <michael.zhu@starfivetech.com> 11 - Drew Fustini <drew@beagleboard.org> 14 StarFive SoC-based boards 21 - items: 22 - enum: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/timer/ |
H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Palmer Dabbelt <palmer@dabbelt.com> 11 - Anup Patel <anup.patel@wdc.com> 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16 interrupts. It directly connects to the timer and inter-processor interrupt 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 19 The clock frequency of CLINT is specified via "timebase-frequency" DT [all …]
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/freebsd/sys/contrib/device-tree/Bindings/serial/ |
H A D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 13 - $ref: serial.yaml# 14 - $ref: rs485.yaml# 16 - if: 20 const: starfive,jh7110-uart 33 - items: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pwm/ |
H A D | opencores,pwm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - William Qiu <william.qiu@starfivetech.com> 14 mode, the PTC core generates binary signal with user-programmable low and 15 high periods. All PTC counters and registers are 32-bit. 18 - $ref: pwm.yaml# 23 - enum: 24 - starfive,jh7100-pwm 25 - starfive,jh7110-pwm [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 represent as any specific type of device. The typical use-case is 13 for some other node's driver, or platform-specific code, to acquire 20 - Lee Jones <lee@kernel.org> 30 - al,alpine-sysfabric-servic 31 - allwinner,sun8i-a83t-system-controller 32 - allwinner,sun8i-h3-system-controller 33 - allwinner,sun8i-v3s-system-controller [all …]
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive Platform-Level Interrupt Controller (PLIC) 11 SiFive SoCs and other RISC-V SoCs include an implementation of the 12 Platform-Level Interrupt Controller (PLIC) high-level specification in 13 the RISC-V Privileged Architecture specification. The PLIC connects all 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 21 Each interrupt can be enabled on per-context basis. Any context can claim [all …]
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