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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
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H A Deukrea-tlv320.txt5 - compatible : "eukrea,asoc-tlv320"
7 - eukrea,model : The user-visible name of this sound complex.
9 - ssi-controller : The phandle of the SSI controller.
11 - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX).
13 - fsl,mux-ext-port : The external port of the i.MX audio muxer.
21 compatible = "eukrea,asoc-tlv320";
22 eukrea,model = "imx51-eukrea-tlv320aic23";
23 ssi-controller = <&ssi2>;
24 fsl,mux-int-port = <2>;
25 fsl,mux-ext-port = <3>;
H A Dfsl,imx-audio-es8328.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,imx-audio-es8328.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
14 - $ref: sound-card-common.yaml#
18 const: fsl,imx-audio-es8328
22 description: The user-visible name of this sound complex
24 ssi-controller:
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H A Dimx-audio-sgtl5000.txt5 - compatible : "fsl,imx-audio-sgtl5000"
7 - model : The user-visible name of this sound complex
9 - ssi-controller : The phandle of the i.MX SSI controller
11 - audio-codec : The phandle of the SGTL5000 audio codec
13 - audio-routing : A list of the connections between audio components.
35 - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
37 - mux-ext-port : The external port of the i.MX audio muxer
45 compatible = "fsl,imx51-babbage-sgtl5000",
46 "fsl,imx-audio-sgtl5000";
47 model = "imx51-babbage-sgtl5000";
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/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux/Documentation/devicetree/bindings/hsi/
H A Domap-ssi.txt1 OMAP SSI controller bindings
3 OMAP3's Synchronous Serial Interface (SSI) controller implements a
5 while the controller found inside OMAP4 is supposed to be fully compliant
9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
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/linux/drivers/hsi/controllers/
H A Domap_ssi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* OMAP SSI internal interface.
23 #define SSI_BYTES_TO_FRAMES(x) ((((x) - 1) >> 2) + 1)
28 * struct omap_ssm_ctx - OMAP synchronous serial module (TX/RX) context
50 * struct omap_ssi_port - OMAP SSI port data
53 * @sst_dma: SSI transmitter physical base address
54 * @ssr_dma: SSI receiver physical base address
55 * @sst_base: SSI transmitter base address
56 * @ssr_base: SSI receiver base address
58 * @lock: Spin lock to serialize access to the SSI port
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H A Domap_ssi_core.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* OMAP SSI driver.
17 #include <linux/dma-mapping.h>
42 struct hsi_controller *ssi = m->private; in ssi_regs_show() local
43 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); in ssi_regs_show()
44 void __iomem *sys = omap_ssi->sys; in ssi_regs_show()
46 pm_runtime_get_sync(ssi->device.parent); in ssi_regs_show()
50 pm_runtime_put(ssi->device.parent); in ssi_regs_show()
57 struct hsi_controller *ssi = m->private; in ssi_gdd_regs_show() local
58 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); in ssi_gdd_regs_show()
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/linux/sound/soc/fsl/
H A Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // This driver implements ASoC support for the Elo DMA controller, which is
10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
16 #include <linux/dma-mapping.h>
39 * The formats that the DMA controller supports, which is anything
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
112 * The PCM hardware is the Freescale DMA controller. This structure defines
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H A Dp1022_rdk.c1 // SPDX-License-Identifier: GPL-2.0
28 /* P1022-specific PMUXCR and DMUXCR bit definitions */
37 #define CCSR_GUTS_DMUXCR_PAD 1 /* DMA controller/channel set to pad */
38 #define CCSR_GUTS_DMUXCR_SSI 2 /* DMA controller/channel set to SSI */
44 * channel on each DMA controller. Rather than have a bunch of repetitive
49 * co: The DMA controller (0 or 1)
50 * ch: The channel on the DMA controller (0, 1, 2, or 3)
56 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); in guts_set_dmuxcr()
58 clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift); in guts_set_dmuxcr()
65 * machine_data: machine-specific ASoC device data
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H A Dp1022_ds.c1 // SPDX-License-Identifier: GPL-2.0
21 /* P1022-specific PMUXCR and DMUXCR bit definitions */
30 #define CCSR_GUTS_DMUXCR_PAD 1 /* DMA controller/channel set to pad */
31 #define CCSR_GUTS_DMUXCR_SSI 2 /* DMA controller/channel set to SSI */
37 * channel on each DMA controller. Rather than have a bunch of repetitive
42 * co: The DMA controller (0 or 1)
43 * ch: The channel on the DMA controller (0, 1, 2, or 3)
49 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); in guts_set_dmuxcr()
51 clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift); in guts_set_dmuxcr()
58 * machine_data: machine-specific ASoC device data
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/linux/arch/mips/boot/dts/ingenic/
H A Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
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H A Dr8a77990.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
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H A Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
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H A Dr8a774b1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774b1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
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H A Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
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H A Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
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H A Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
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H A Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
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/linux/drivers/spi/
H A Dspi-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/spi/spi-mem.h>
14 /* Synopsys DW SSI IP-core virtual IDs */
18 /* Synopsys DW SSI component versions (FourCC sequence) */
21 /* DW SSI IP-core ID and version check helpers */
23 ((_dws)->ip == DW_ ## _ip ## _ID)
26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
32 /* DW SPI controller capabilities */
36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
65 /* Bit fields in CTRLR0 (DWC APB SSI) */
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H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
58 if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) in dw_spi_bt1_dirmap_create()
59 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
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H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
24 #include "spi-dw.h"
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
61 * bit: |---3-------2-------1-------0
71 * The Designware SPI controller (referred to as master in the documentation)
74 * the SPI boot controller registers. the final chip select is an OR gate
75 * between the Designware SPI controller and the SPI boot controller.
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
81 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx27-pinfunc.h"
7 #include <dt-bindings/clock/imx27-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
43 aitc: aitc-interrupt-controller@10040000 {
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