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/linux/drivers/hid/
H A Dhid-saitek.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Fixes the HID report descriptor by removing a non-existent axis and
7 * clearing the constant bit on the input reports for buttons and d-pad.
8 * (This module is based on "hid-ortek".)
12 * Fixes the mode button which cycles through three constantly pressed
25 #include "hid-ids.h"
33 int mode; member
39 unsigned long quirks = id->driver_data; in saitek_probe()
40 struct saitek_sc *ssc; in saitek_probe() local
43 ssc = devm_kzalloc(&hdev->dev, sizeof(*ssc), GFP_KERNEL); in saitek_probe()
[all …]
/linux/include/linux/
H A Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
134 /* SSC Receive Hold Register */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Datmel,at91-ssc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/atmel,at91-ssc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Serial Synchronous Serial (SSC)
10 - Andrei Simion <andrei.simion@microchip.com>
13 The Atmel Synchronous Serial Controller (SSC) provides a versatile
20 - enum:
21 - atmel,at91rm9200-ssc
22 - atmel,at91sam9g45-ssc
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/linux/drivers/scsi/isci/
H A Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
200 * MPC Manual PORT configuration mode is defined by the OEM configuration
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
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/linux/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI host mode controller driver, used in STMicroelectronics devices.
25 /* SSC registers */
33 /* SSC Control */
48 /* SSC Interrupt Enable */
54 /* SSC SPI Controller */
59 /* SSC SPI current transaction */
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
[all …]
/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
29 * struct dpll_data - DPLL registers and integration data
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45 * @min_divider: minimum valid non-bypass divider value (actual)
46 * @max_divider: maximum valid non-bypass divider value (actual)
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
58 /* PLL Test Mode register parameters */
62 /* PLL SSC step size offsets */
71 /* SSC step size parameters */
136 /* Test Mode common reset control parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
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/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
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/linux/sound/soc/atmel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"
23 Say Y or M if you want to add support for Atmel SSC interface
24 in PDC mode configured using audio-graph-card in device-tree.
27 tristate "SoC PCM DAI support for AT91 SSC controller using DMA"
32 Say Y or M if you want to add support for Atmel SSC interface
33 in DMA mode configured using audio-graph-card in device-tree.
36 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
42 Say Y if you want to add support for SoC audio on WM8731-based
56 tristate "SoC Audio support for WM8731-based at91sam9x5 board"
[all …]
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
84 /* ports 1-3 follow after this */
87 /* ports 5-7 follow after this */
91 /* phys 1-3 follow after this */
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/linux/drivers/mmc/host/
H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
468 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
481 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
483 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
484 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
488 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
19 - rockchip,rk3588-naneng-combphy
[all …]
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
[all …]
H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dmpa1600.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * mpa1600.dts - Device Tree file for Phontech MPA 1600
7 /dts-v1/;
20 clock-frequency = <32768>;
24 clock-frequency = <18432000>;
36 compatible = "atmel,tcb-timer";
41 compatible = "atmel,tcb-timer";
47 phy-mode = "rmii";
51 ssc0: ssc@fffd0000 {
55 ssc1: ssc@fffd4000 {
[all …]
H A Dat91rm9200.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
[all …]
H A Dat91sam9261.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 #include <dt-bindings/pinctrl/at91.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dat91sam9g20ek_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <dt-bindings/input/input.h>
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <18432000>;
50 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
63 compatible = "atmel,tcb-timer";
68 compatible = "atmel,tcb-timer";
[all …]
H A Dat91-sama5d4ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
8 /dts-v1/;
12 model = "Atmel SAMA5D4-EK";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
36 pinctrl-names = "default";
37 pinctrl-0 = <
45 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
[all …]
/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
386 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
[all …]
/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
98 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
101 regmap_write(phy->regmap, reg, val); in mt7621_phy_rmw()
109 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
119 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
122 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
124 return -EINVAL; in mt7621_set_phy_for_ssc()
126 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
[all …]
/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
202 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
203 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-acpi@vger.kernel.org
19 Contact: linux-acpi@vger.kernel.org
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-acpi@vger.kernel.org
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