Searched full:sregs (Results 1 – 9 of 9) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/arm/calxeda/ |
H A D | hb-sregs.yaml | 4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml# 19 const: calxeda,hb-sregs 35 sregs@fff3c000 { 36 compatible = "calxeda,hb-sregs";
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H A D | l2ecc.yaml | 19 const: calxeda,hb-sregs-l2-ecc 38 sregs@fff3c200 { 39 compatible = "calxeda,hb-sregs-l2-ecc";
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | calxeda.yaml | 13 "hb-sregs" node. 45 sregs@3fffc000 { 46 compatible = "calxeda,hb-sregs";
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 1562 BitVector SRegs(Hexagon::NUM_TARGET_REGS); in assignCalleeSavedSpillSlots() local 1564 // Generate a set of unique, callee-saved registers (SRegs), where each in assignCalleeSavedSpillSlots() 1566 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs. in assignCalleeSavedSpillSlots() 1569 // sub-registers to SRegs. in assignCalleeSavedSpillSlots() 1575 SRegs[SR] = true; in assignCalleeSavedSpillSlots() 1578 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); in assignCalleeSavedSpillSlots() 1582 // sub- and super-registers from SRegs. in assignCalleeSavedSpillSlots() 1607 SRegs[SR] = false; in assignCalleeSavedSpillSlots() 1611 LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); in assignCalleeSavedSpillSlots() 1614 // (3) Collect all registers that have at least one sub-register in SRegs, in assignCalleeSavedSpillSlots() [all …]
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/freebsd/sys/contrib/device-tree/src/arm/calxeda/ |
H A D | highbank.dts | 149 sregs@fff3c200 { 150 compatible = "calxeda,hb-sregs-l2-ecc";
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H A D | ecx-common.dtsi | 131 sregs@fff3c000 { 132 compatible = "calxeda,hb-sregs";
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulationStateARM.h | 69 uint32_t s_regs[32]; // sregs 0 - 31 & dregs 0 - 15
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/freebsd/contrib/libpcap/msdos/ |
H A D | pktdrvr.c | 321 struct SREGS s; in PktInterrupt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 6080 SmallVector<Register, 8> SRegs; in readlaneVGPRToSGPR() local 6086 SRegs.push_back(SGPR); in readlaneVGPRToSGPR() 6093 MIB.addReg(SRegs[i]); in readlaneVGPRToSGPR()
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