| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() local
60 switch (device->chipset) { in read_pll_src()
73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); in read_pll_src()
74 ref *= (coef & 0x01000000) ? 2 : 4; in read_pll_src()
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
76 N = ((coef & 0x0000ff00) >> 8) + 1; in read_pll_src()
[all …]
|
| H A D | nv40.c | 42 struct nvkm_device *device = clk->base.subdev.device; in read_pll_1()
58 struct nvkm_device *device = clk->base.subdev.device; in read_pll_2()
60 u32 coef = nvkm_rd32(device, reg + 0x04); in read_pll_2() local
61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2()
63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2()
64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
84 switch (src) { in read_clk()
97 nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in nv40_clk_read() argument
[all …]
|
| H A D | gf100.c | 38 u32 coef; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
63 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
64 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
65 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
66 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
75 sclk = device->crystal; in read_pll()
[all …]
|
| H A D | gk104.c | 38 u32 coef; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
77 sclk = device->crystal; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
[all …]
|
| H A D | gt215.c | 45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
117 u32 coef = nvkm_rd32(device, pll + 4); in read_pll() local
118 M = (coef & 0x000000ff) >> 0; in read_pll()
119 N = (coef & 0x0000ff00) >> 8; in read_pll()
[all …]
|
| H A D | mcp77.c | 44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); in read_pll() local
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
89 switch (src) { in mcp77_clk_read()
[all …]
|
| /linux/drivers/media/platform/st/sti/bdisp/ |
| H A D | bdisp-hw.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "bdisp-filter.h"
11 #include "bdisp-reg.h"
27 bool cconv; /* RGB - YUV conversion */
34 bool src_interlaced; /* is the src an interlaced buffer */
35 u8 src_nbp; /* nb of planes of the src */
36 bool src_yuv; /* is the src a YUV color format */
37 bool src_420; /* is the src 4:2:0 chroma subsampled */
54 .coef = {
68 .coef = {
[all …]
|
| /linux/drivers/dma/ioat/ |
| H A D | prep.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2004 - 2015 Intel Corporation.
10 #include <linux/dma-mapping.h>
36 raw->field[xor_idx_to_field[idx]] = addr + offset; in xor_set_src()
43 return raw->field[pq_idx_to_field[idx]]; in pq_get_src()
50 return raw->field[pq16_idx_to_field[idx]]; in pq16_get_src()
54 dma_addr_t addr, u32 offset, u8 coef, int idx) in pq_set_src() argument
59 raw->field[pq_idx_to_field[idx]] = addr + offset; in pq_set_src()
60 pq->coef[idx] = coef; in pq_set_src()
64 dma_addr_t addr, u32 offset, u8 coef, unsigned idx) in pq16_set_src() argument
[all …]
|
| /linux/include/linux/mfd/ |
| H A D | ac100.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
91 #define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */
92 #define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */
93 #define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */
94 #define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */
100 #define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */
101 #define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */
102 #define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | mediatek,xsphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
[all …]
|
| H A D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
[all …]
|
| /linux/sound/hda/codecs/cirrus/ |
| H A D | cs420x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cirrus Logic CS420x HD-audio codec
52 /* Vendor-specific processing widget */
59 /* coef indices */
65 * 1 = digital immediate, analog zero-cross
66 * 2 = digtail & analog soft-ram
105 cs_vendor_coef_set(struct hda_codec * codec,unsigned int idx,unsigned int coef) cs_vendor_coef_set() argument
150 unsigned int coef; init_input_coef() local
241 unsigned int coef; init_digital_coef() local
[all...] |
| /linux/drivers/dma/ |
| H A D | fsl_raid.c | 13 * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
67 #include <linux/dma-mapping.h>
86 /* Add descriptors into per chan software queue - submit_q */
95 re_chan = container_of(tx->chan, struct fsl_re_chan, chan); in fsl_re_tx_submit()
97 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
99 list_add_tail(&desc->node, &re_chan->submit_q); in fsl_re_tx_submit()
100 spin_unlock_irqrestore(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
115 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_issue_pending()
117 in_be32(&re_chan->jrregs->inbring_slot_avail)); in fsl_re_issue_pending()
119 list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) { in fsl_re_issue_pending()
[all …]
|
| /linux/drivers/media/platform/rockchip/rkvdec/ |
| H A D | rkvdec-vp9.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Alpha Lin <Alpha.Lin@rock-chips.com>
21 #include <media/v4l2-mem2mem.h>
22 #include <media/v4l2-vp9.h>
25 #include "rkvdec-regs.h"
49 u8 coef[2][4][2][128]; member
169 static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane) in write_coeff_plane()
178 p = coef[k][m][n]; in write_coeff_plane()
193 struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; in init_intra_only_probs()
194 struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; in init_intra_only_probs()
[all …]
|
| /linux/drivers/dma/ppc4xx/ |
| H A D | adma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2009 DENX Software Engineering.
22 #include <linux/dma-mapping.h>
33 #include <asm/dcr-regs.h>
91 /* This array is used in data-check operations for storing a pattern */
98 /* Since RXOR operations use the common register (MQ0_CF2H) for setting-up
135 switch (chan->device->id) { in print_cb()
145 cdb, chan->device->id, in print_cb()
146 cdb->attr, cdb->opc, le32_to_cpu(cdb->cnt), in print_cb()
147 le32_to_cpu(cdb->sg1u), le32_to_cpu(cdb->sg1l), in print_cb()
[all …]
|
| /linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | main.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
440 /* the power index is represented by differences, which cck-1s & ht40-1s are
809 /* SU-MIMO */
812 /* MU-MIMO */
1109 (*tbl->parse)(rtwdev, tbl); in rtw_load_table()
1502 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1614 u32 coef[RTW_RF_PATH_MAX][20]; member
1953 * which might not re-use same format with array common.
[all …]
|