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/linux/drivers/misc/
H A Dsram.c3 * Generic on-chip SRAM allocation driver
21 #include "sram.h"
55 static int sram_add_pool(struct sram_dev *sram, struct sram_reserve *block, in sram_add_pool() argument
60 part->pool = devm_gen_pool_create(sram->dev, ilog2(SRAM_GRANULARITY), in sram_add_pool()
68 dev_err(sram->dev, "failed to register subpool: %d\n", ret); in sram_add_pool()
75 static int sram_add_export(struct sram_dev *sram, struct sram_reserve *block, in sram_add_export() argument
79 part->battr.attr.name = devm_kasprintf(sram->dev, GFP_KERNEL, in sram_add_export()
80 "%llx.sram", in sram_add_export()
90 return device_create_bin_file(sram->dev, &part->battr); in sram_add_export()
93 static int sram_add_partition(struct sram_dev *sram, struct sram_reserve *block, in sram_add_partition() argument
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H A Dsram-exec.c3 * SRAM protect-exec region helper functions
12 #include <linux/sram.h>
17 #include "sram.h"
22 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
29 dev_err(sram->dev, in sram_check_protect_exec()
30 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
47 * sram_exec_copy - copy data to a protected executable region of sram
49 * @pool: struct gen_pool retrieved that is part of this sram
57 * This helper function allows sram driver to act as central control location
58 * of 'protect-exec' pools which are normal sram pools but are always set
/linux/arch/arm/mach-omap1/
H A Dsram-init.c3 * OMAP SRAM detection and management
22 #include "sram.h"
35 * Memory allocator for SRAM: calculates the new ceiling address
48 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
61 void *sram; in omap_sram_push() local
66 sram = omap_sram_push_address(size); in omap_sram_push()
67 if (!sram) in omap_sram_push()
70 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
75 dst = fncpy(sram, funcp, size); in omap_sram_push()
83 * The amount of SRAM depends on the core type.
[all …]
/linux/arch/arm/mach-omap2/
H A Dsram.c4 * OMAP SRAM detection and management
29 #include "sram.h"
57 * Memory allocator for SRAM: calculates the new ceiling address
70 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
83 void *sram; in omap_sram_push() local
88 sram = omap_sram_push_address(size); in omap_sram_push()
89 if (!sram) in omap_sram_push()
92 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
97 dst = fncpy(sram, funcp, size); in omap_sram_push()
105 * The SRAM context is lost during off-idle and stack
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/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4357.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst29 the system SRAM) for different peripheral. It can access external RAMs but
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
113 bad with DDR, while they are optimal with SRAM. Hence the SRAM buffer used
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
140 **1. Allocate a SRAM buffer**
142 SRAM device tree node is defined in SoC device tree. You can refer to it in
143 your board device tree to define your SRAM pool.
146 &sram {
147 my_foo_device_dma_pool: dma-sram@0 {
152 Be careful of the start index, in case there are other SRAM consumers.
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/linux/drivers/mtd/devices/
H A Dms02-nv.h16 * 0x000000 - 0x3fffff SRAM
19 * Within the SRAM area the following ranges are forced by the system
28 * ID value is found, the firmware considers the SRAM clean, i.e.
38 * as well as the size of SRAM available, which can be 1MiB or 2MiB
44 * stored in the SRAM cannot be relied upon. But from the hardware
74 #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */
75 #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */
76 #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */
77 #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */
78 #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */
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/linux/arch/arm/mach-davinci/
H A Dsram.h3 * mach/sram.h - DaVinci simple SRAM allocator
10 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14 * SRAM allocations return a CPU virtual address, or NULL on error.
15 * If a DMA address is requested and the SRAM supports DMA, its
18 * Errors include SRAM memory not being available, and requesting
19 * DMA mapped SRAM on systems which don't allow that.
/linux/Documentation/devicetree/bindings/crypto/
H A Dmv_cesa.txt9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;
H A Dmarvell-cesa.txt13 region. Can also contain an entry for the SRAM attached to the CESA,
16 - reg-names: "regs". Can contain an "sram" entry, but this representation
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
43 marvell,crypto-sram-size = <0x600>;
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dmtk,scp.yaml29 Should contain the address ranges for memory regions SRAM, CFG, and,
81 local SCP SRAM address spaces to bus addresses.
93 Each SCP core has own cache memory. The SRAM and L1TCM are shared by
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
109 description: The base address and size of SRAM.
113 const: sram
177 - const: sram
191 - const: sram
220 reg-names = "sram", "cfg", "l1tcm";
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H A Damlogic,meson-mx-ao-arc.yaml50 sram:
53 phandles to a reserved SRAM region which is used as the memory of
55 AHB SRAM node as per the generic bindings in
56 Documentation/devicetree/bindings/sram/sram.yaml
70 - sram
83 sram = <&ahb_sram_ao_arc>;
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pm.c12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
24 static void __iomem *sram; variable
81 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ in mpc52xx_pm_prepare()
93 sram = mbar + 0x8000; /* Those will be handled by the */ in mpc52xx_pm_prepare()
134 /* save SRAM */ in mpc52xx_pm_enter()
135 memcpy(saved_sram, sram, sram_size); in mpc52xx_pm_enter()
137 /* copy low level suspend code to sram */ in mpc52xx_pm_enter()
138 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size); in mpc52xx_pm_enter()
144 /* disable all but SDRAM and bestcomm (SRAM) clocks */ in mpc52xx_pm_enter()
162 mpc52xx_deep_sleep(sram, sdram, cdm, intr); in mpc52xx_pm_enter()
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/linux/drivers/fsi/
H A Dfsi-master-ast-cf.c82 /* Amount of SRAM required */
111 void __iomem *sram; member
315 iowrite32be(op, master->sram + CMD_STAT_REG); in do_copro_command()
328 stat = ioread8(master->sram + CMD_STAT_REG); in do_copro_command()
365 /* Store message into SRAM */ in send_request()
366 iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA); in send_request()
367 iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4); in send_request()
380 uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf; in read_copro_response()
381 uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf; in read_copro_response()
392 rdata = ioread32be(master->sram + RSP_DATA); in read_copro_response()
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/linux/drivers/memory/
H A Dti-emif-pm.c3 * TI AM33XX SRAM EMIF Driver
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
69 emif_data->sram_pool_code = of_gen_pool_get(np, "sram", 0); in ti_emif_alloc_sram()
71 dev_err(dev, "Unable to get sram pool for ocmcram code\n"); in ti_emif_alloc_sram()
88 /* Get sram pool for data section and allocate space */ in ti_emif_alloc_sram()
89 emif_data->sram_pool_data = of_gen_pool_get(np, "sram", 1); in ti_emif_alloc_sram()
91 dev_err(dev, "Unable to get sram pool for ocmcram data\n"); in ti_emif_alloc_sram()
158 dev_err(dev, "Cannot copy emif code to sram\n"); in ti_emif_push_sram()
169 dev_err(dev, "Cannot copy emif data to code sram\n"); in ti_emif_push_sram()
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/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-orion-net.txt43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dcanaan,k210-sram.yaml4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
20 - canaan,k210-sram
47 compatible = "canaan,k210-sram";
/linux/drivers/soc/sunxi/
H A Dsunxi_sram.c2 * Allwinner SoCs SRAM Controller Driver
86 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
90 .compatible = "allwinner,sun4i-a10-sram-c1",
94 .compatible = "allwinner,sun4i-a10-sram-d",
98 .compatible = "allwinner,sun50i-a64-sram-c",
117 seq_puts(s, "Allwinner sunXi SRAM\n"); in sunxi_sram_show()
121 if (!of_device_is_compatible(sram_node, "mmio-sram")) in sunxi_sram_show()
126 seq_printf(s, "sram@%08x\n", in sunxi_sram_show()
176 ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0, in sunxi_sram_of_parse()
387 debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops); in sunxi_sram_probe()
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/linux/drivers/media/common/b2c2/
H A Dflexcop-sram.c4 * flexcop-sram.c - functions for controlling the SRAM
38 err("SRAM destination target to available on FlexCopII(b)\n"); in flexcop_sram_set_dest()
41 deb_sram("sram dest: %x target: %x\n", dest, target); in flexcop_sram_set_dest()
92 printk("%s: SRAM timeout\n", __func__);
117 printk("%s: SRAM timeout\n", __func__);
129 printk("%s: SRAM timeout\n", __func__);
293 /* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.
318 // check for internal SRAM ???
324 dprintk("%s: sram size = 32K\n", __func__);
332 dprintk("%s: sram size = 128K\n", __func__);
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/linux/drivers/media/pci/cx25821/
H A Dcx25821-sram.h12 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
17 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */
26 /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */
27 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
29 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
36 /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */
37 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
39 /* Receive SRAM */
167 /* Free Receive SRAM 144 Bytes */
169 /* Transmit SRAM */
/linux/drivers/crypto/ccree/
H A Dcc_sram_mgr.h16 * cc_sram_mgr_init() - Initializes SRAM pool.
17 * The first X bytes of SRAM are reserved for ROM usage, hence, pool
28 * cc_sram_alloc() - Allocate buffer from SRAM pool.
34 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
40 * set values in given array into SRAM.
44 * @dst: The target SRAM buffer to set into
H A Dcc_sram_mgr.c8 * cc_sram_mgr_init() - Initializes SRAM pool.
9 * The pool starts right at the beginning of SRAM.
26 dev_err(dev, "Invalid SRAM offset 0x%x\n", start); in cc_sram_mgr_init()
36 * cc_sram_alloc() - Allocate buffer from SRAM pool.
42 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
68 * set values in given array into SRAM.
72 * @dst: The target SRAM buffer to set into
/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c60 * struct zynqmp_sram_bank - sram bank description
62 * @sram_res: sram address region information
63 * @da: device address of sram
134 * @sram: Array of sram memories assigned to this core
135 * @num_sram: number of sram for this core
147 struct zynqmp_sram_bank *sram; member
516 struct zynqmp_sram_bank *sram; in add_sram_carveouts() local
522 sram = &r5_core->sram[i]; in add_sram_carveouts()
524 dma_addr = (dma_addr_t)sram->sram_res.start; in add_sram_carveouts()
526 len = resource_size(&sram->sram_res); in add_sram_carveouts()
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dfsl,mu.yaml110 "^sram@[a-f0-9]+":
111 $ref: /schemas/sram/sram.yaml#
148 "^sram@[a-f0-9]+": false
175 sram@445b1000 {
176 compatible = "mmio-sram";
182 scmi-sram-section@0 {
187 scmi-sram-section@80 {

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