| /freebsd/sys/contrib/device-tree/Bindings/sram/ |
| H A D | sram.yaml | 4 $id: http://devicetree.org/schemas/sram/sram.yaml#
7 title: Generic on-chip SRAM
15 Each child of the sram node specifies a region of reserved memory. Each
25 pattern: "^sram(@.*)?"
30 - mmio-sram
31 - amlogic,meson-gxbb-sram
32 - arm,juno-sram-ns
38 - rockchip,rk3288-pmu-sram
47 SRAM clock.
58 Should translate from local addresses within the sram to bus addresses.
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| H A D | allwinner,sun4i-a10-system-control.yaml | 4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
28 - allwinner,sun4i-a10-sram-controller
29 - allwinner,sun50i-a64-sram-controller
62 "^sram@[a-f0-9]+":
63 $ref: /schemas/sram/sram.yaml#
67 "^sram-section?@[a-f0-9]+$":
76 - const: allwinner,sun4i-a10-sram-a3-a4
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | cache_sram.txt | 1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/ |
| H A D | lpc4350.dtsi | 24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
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| H A D | lpc4357.dtsi | 24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
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| /freebsd/sys/contrib/device-tree/Bindings/crypto/ |
| H A D | mv_cesa.txt | 9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;
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| H A D | marvell-cesa.txt | 13 region. Can also contain an entry for the SRAM attached to the CESA,
16 - reg-names: "regs". Can contain an "sram" entry, but this representation
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
43 marvell,crypto-sram-size = <0x600>;
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| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | mtk,scp.yaml | 29 Should contain the address ranges for memory regions SRAM, CFG, and,
81 local SCP SRAM address spaces to bus addresses.
93 Each SCP core has own cache memory. The SRAM and L1TCM are shared by
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
109 description: The base address and size of SRAM.
113 const: sram
177 - const: sram
191 - const: sram
220 reg-names = "sram", "cfg", "l1tcm";
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| H A D | amlogic,meson-mx-ao-arc.yaml | 50 sram:
53 phandles to a reserved SRAM region which is used as the memory of
55 AHB SRAM node as per the generic bindings in
56 Documentation/devicetree/bindings/sram/sram.yaml
70 - sram
83 sram = <&ahb_sram_ao_arc>;
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| H A D | ti,k3-dsp-rproc.yaml | 77 sram:
84 phandles to one or more reserved on-chip SRAM regions. The regions
85 should be defined as child nodes of the respective SRAM node, and
87 Documentation/devicetree/bindings/sram/sram.yaml
99 - description: Address and Size of the L2 SRAM internal memory region
118 - description: Address and Size of the L2 SRAM internal memory region
134 - description: Address and Size of the L2 SRAM internal memory region
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | marvell-orion-net.txt | 43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
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| H A D | allwinner,sun4i-a10-emac.yaml | 29 allwinner,sram:
30 description: Phandle to the device SRAM
34 - description: phandle to SRAM
43 - allwinner,sram
55 allwinner,sram = <&emac_sram 1>;
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | canaan,k210-sram.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
20 - canaan,k210-sram
47 compatible = "canaan,k210-sram";
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| H A D | arm,pl353-smc.yaml | 16 SRAM or NOR).
66 - description: NOR/SRAM bank 0
67 - description: NOR/SRAM bank 1
77 mapped controllers such as NOR and SRAM controllers.
119 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
120 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | fsl,mu.yaml | 110 "^sram@[a-f0-9]+":
111 $ref: /schemas/sram/sram.yaml#
148 "^sram@[a-f0-9]+": false
175 sram@445b1000 {
176 compatible = "mmio-sram";
182 scmi-sram-section@0 {
187 scmi-sram-section@80 {
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,scpi.txt | 59 SRAM and Shared Memory for SCPI
62 A small area of SRAM is reserved for SCPI communication between application
65 The properties should follow the generic mmio-sram description found in [3]
70 - reg : The base offset and size of the reserved area with the SRAM
71 - compatible : should be "arm,scp-shmem" for Non-secure SRAM based
112 [3] Documentation/devicetree/bindings/sram/sram.yaml
117 sram: sram@50000000 {
118 compatible = "arm,juno-sram-ns", "mmio-sram";
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| H A D | juno,scpi.txt | 4 Juno SRAM and Shared Memory for SCPI
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
|
| H A D | arm,scmi.txt | 109 SRAM and Shared Memory for SCMI
112 A small area of SRAM is reserved for SCMI communication between application
115 The properties should follow the generic mmio-sram description found in [4]
120 - reg : The base offset and size of the reserved area with the SRAM
121 - compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
128 [4] Documentation/devicetree/bindings/sram/sram.yaml
134 sram@50000000 {
135 compatible = "mmio-sram";
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| /freebsd/sys/contrib/device-tree/Bindings/arm/omap/ |
| H A D | mpu.txt | 14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
52 pm-sram = <&pm_sram_code
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | hi6220-clock.txt | 28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
29 the driver need use the sram to pass parameters for frequency change.
44 hisilicon,hi6220-clk-sram = <&sram>;
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| /freebsd/sys/contrib/device-tree/src/arm64/arm/ |
| H A D | juno-scmi.dtsi | 200 &sram {
201 /delete-node/ scp-sram@0;
202 /delete-node/ scp-sram@200;
204 cpu_scp_lpri0: scp-sram@0 {
209 cpu_scp_lpri1: scp-sram@80 {
214 cpu_scp_hpri0: scp-sram@100 {
219 cpu_scp_hpri1: scp-sram@180 {
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_aic.c | 45 struct ath_aic_sram_info sram; member
413 /* From dir/quad_path_gain_lin to sram. */ in ar9300_aic_cal_post_process()
426 aic_sram[i].sram.vga_dir_sign = (aic_sram[i].dir_path_gain_lin >= 0) in ar9300_aic_cal_post_process()
428 aic_sram[i].sram.vga_quad_sign= (aic_sram[i].quad_path_gain_lin >= 0) in ar9300_aic_cal_post_process()
438 aic_sram[i].sram.com_att_6db = ar9300_aic_find_index(1, in ar9300_aic_cal_post_process()
441 aic_sram[i].sram.valid = 1; in ar9300_aic_cal_post_process()
442 aic_sram[i].sram.rot_dir_att_db = in ar9300_aic_cal_post_process()
445 aic_sram[i].sram.rot_quad_att_db = in ar9300_aic_cal_post_process()
453 ahp->ah_aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign, in ar9300_aic_cal_post_process()
455 SM(aic_sram[i].sram.vga_quad_sign, in ar9300_aic_cal_post_process()
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | allwinner,sun4i-a10-video-engine.yaml | 49 allwinner,sram:
53 - description: phandle to SRAM
55 description: Phandle to the device SRAM
73 - allwinner,sram
91 allwinner,sram = <&ve_sram 1>;
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | allwinner,sun50i-a64-de2.yaml | 33 allwinner,sram:
35 The SRAM that needs to be claimed to access the display engine
40 - description: phandle to SRAM
63 - allwinner,sram
72 allwinner,sram = <&de2_sram 1>;
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| /freebsd/sys/contrib/device-tree/src/arm/allwinner/ |
| H A D | sun5i.dtsi | 140 sram_a: sram@0 {
141 compatible = "mmio-sram";
147 emac_sram: sram-section@8000 {
148 compatible = "allwinner,sun5i-a13-sram-a3-a4",
149 "allwinner,sun4i-a10-sram-a3-a4";
155 sram_d: sram@10000 {
156 compatible = "mmio-sram";
162 otg_sram: sram-section@0 {
163 compatible = "allwinner,sun5i-a13-sram-d",
164 "allwinner,sun4i-a10-sram-d";
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