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Searched +full:sr +full:- +full:cdru (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm,sr-pcie-phy.txt4 - compatible: must be "brcm,sr-pcie-phy"
5 - reg: base address and length of the PCIe SS register space
6 - brcm,sr-cdru: phandle to the CDRU syscon node
7 - brcm,sr-mhb: phandle to the MHB syscon node
8 - #phy-cells: Must be 1, denotes the PHY index
17 compatible = "brcm,sr-mhb", "syscon";
21 cdru: syscon@6641d000 {
22 compatible = "brcm,sr-cdru", "syscon";
27 compatible = "brcm,sr-pcie-phy";
29 brcm,sr-cdru = <&cdru>;
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H A Dbrcm,sr-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sr-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
20 const: brcm,sr-pcie-phy
25 '#phy-cells':
28 brcm,sr-cdru:
29 description: phandle to the CDRU syscon node
32 brcm,sr-mhb:
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dbrcm,iproc-cdru.txt1 Broadcom iProc Chip Device Resource Unit (CDRU)
5 these CDRU registers via syscon.
8 - compatible: should contain:
9 "brcm,sr-cdru", "syscon" for Stingray
10 - reg: base address and range of the CDRU registers
13 cdru: syscon@6641d000 {
14 compatible = "brcm,sr-cdru", "syscon";
H A Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
30 - airoha,en7581-pbus-csr
31 - al,alpine-sysfabric-service
32 - allwinner,sun8i-a83t-system-controller
33 - allwinner,sun8i-h3-system-controller
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pcie.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
7 compatible = "brcm,iproc-pcie-paxc-v2";
9 linux,pci-domain = <8>;
11 bus-rang
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H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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