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Searched +full:spum +full:- +full:crypto (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dbrcm,spum-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/brcm,spum-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPU Crypto Offload
10 - Rob Rice <rob.rice@broadcom.com>
20 - brcm,spum-crypto
21 - brcm,spu2-crypto
22 …- brcm,spu2-v2-crypto # enhanced SPU2 hardware features like SHA3 and Rabin Fingerprint support
23 - brcm,spum-nsp-crypto # Northstar Plus variant of the SPU-M hardware
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H A Dbrcm,spu-crypto.txt6 - compatible: Should be one of the following:
7 brcm,spum-crypto - for devices with SPU-M hardware
8 brcm,spu2-crypto - for devices with SPU2 hardware
9 brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
11 brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
13 - reg: Should contain SPU registers location and length.
14 - mboxes: The mailbox channel to be used to communicate with the SPU.
18 crypto@612d0000 {
19 compatible = "brcm,spum-crypto";
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-paren
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