1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) 8 9maintainers: 10 - Siddharth Vadapalli <s-vadapalli@ti.com> 11 - Roger Quadros <rogerq@kernel.org> 12 13description: 14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports 15 (one external) and provides Ethernet packet communication for the device. 16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports 17 (two external) and provides Ethernet packet communication and switching. 18 19 The internal Communications Port Programming Interface (CPPI5) (Host port 0). 20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels 21 and one RX channels and operating by NAVSS Unified DMA Peripheral Root 22 Complex (UDMA-P) controller. 23 24 CPSWxG features 25 updated Address Lookup Engine (ALE). 26 priority level Quality Of Service (QOS) support (802.1p) 27 Support for Audio/Video Bridging (P802.1Qav/D6.0) 28 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) 29 Flow Control (802.3x) Support 30 Time Sensitive Network Support 31 IEEE P902.3br/D2.0 Interspersing Express Traffic 32 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic 33 Configurable number of addresses plus VLANs 34 Configurable number of classifier/policers 35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on 36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size. 37 RX/TX csum offload 38 Management Data Input/Output (MDIO) interface for PHYs management 39 RMII/RGMII Interfaces support 40 new version of Common Platform Time Sync (CPTS) 41 42 The CPSWxG NUSS is integrated into 43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC. 44 device MAIN domain named CPSW0 on AM642x SoC. 45 46 Specifications can be found at 47 https://www.ti.com/lit/pdf/spruid7 48 https://www.ti.com/lit/zip/spruil1 49 https://www.ti.com/lit/pdf/spruim2 50 51properties: 52 "#address-cells": true 53 "#size-cells": true 54 55 compatible: 56 enum: 57 - ti,am642-cpsw-nuss 58 - ti,am654-cpsw-nuss 59 - ti,j7200-cpswxg-nuss 60 - ti,j721e-cpsw-nuss 61 - ti,j721e-cpswxg-nuss 62 - ti,j784s4-cpswxg-nuss 63 64 reg: 65 maxItems: 1 66 description: 67 The physical base address and size of full the CPSWxG NUSS IO range 68 69 reg-names: 70 items: 71 - const: cpsw_nuss 72 73 ranges: true 74 75 dma-coherent: true 76 77 clocks: 78 maxItems: 1 79 description: CPSWxG NUSS functional clock 80 81 clock-names: 82 items: 83 - const: fck 84 85 assigned-clock-parents: true 86 87 assigned-clocks: true 88 89 power-domains: 90 maxItems: 1 91 92 dmas: 93 maxItems: 9 94 95 dma-names: 96 items: 97 - const: tx0 98 - const: tx1 99 - const: tx2 100 - const: tx3 101 - const: tx4 102 - const: tx5 103 - const: tx6 104 - const: tx7 105 - const: rx 106 107 ethernet-ports: 108 type: object 109 properties: 110 '#address-cells': 111 const: 1 112 '#size-cells': 113 const: 0 114 115 patternProperties: 116 "^port@[1-8]$": 117 type: object 118 description: CPSWxG NUSS external ports 119 120 $ref: ethernet-controller.yaml# 121 unevaluatedProperties: false 122 123 properties: 124 reg: 125 minimum: 1 126 maximum: 8 127 description: CPSW port number 128 129 phys: 130 minItems: 1 131 items: 132 - description: CPSW MAC's PHY. 133 - description: Serdes PHY. Serdes PHY is required only if 134 the Serdes has to be configured in the 135 Single-Link configuration. 136 137 phy-names: 138 minItems: 1 139 items: 140 - const: mac 141 - const: serdes 142 143 label: 144 description: label associated with this port 145 146 fixed-link: true 147 148 ti,mac-only: 149 $ref: /schemas/types.yaml#/definitions/flag 150 description: 151 Specifies the port works in mac-only mode. 152 153 ti,syscon-efuse: 154 $ref: /schemas/types.yaml#/definitions/phandle-array 155 items: 156 - items: 157 - description: Phandle to the system control device node which 158 provides access to efuse 159 - description: offset to efuse registers??? 160 description: 161 Phandle to the system control device node which provides access 162 to efuse IO range with MAC addresses 163 164 required: 165 - reg 166 - phys 167 168 additionalProperties: false 169 170patternProperties: 171 "^mdio@[0-9a-f]+$": 172 type: object 173 $ref: ti,davinci-mdio.yaml# 174 175 description: 176 CPSW MDIO bus. 177 178 "^cpts@[0-9a-f]+": 179 type: object 180 $ref: ti,k3-am654-cpts.yaml# 181 description: 182 CPSW Common Platform Time Sync (CPTS) module. 183 184required: 185 - compatible 186 - reg 187 - reg-names 188 - ranges 189 - clocks 190 - clock-names 191 - power-domains 192 - dmas 193 - dma-names 194 - '#address-cells' 195 - '#size-cells' 196 197allOf: 198 - if: 199 not: 200 properties: 201 compatible: 202 contains: 203 enum: 204 - ti,j721e-cpswxg-nuss 205 - ti,j784s4-cpswxg-nuss 206 then: 207 properties: 208 ethernet-ports: 209 patternProperties: 210 "^port@[5-8]$": false 211 "^port@[1-4]$": 212 properties: 213 reg: 214 minimum: 1 215 maximum: 4 216 217 - if: 218 not: 219 properties: 220 compatible: 221 contains: 222 enum: 223 - ti,j7200-cpswxg-nuss 224 - ti,j721e-cpswxg-nuss 225 - ti,j784s4-cpswxg-nuss 226 then: 227 properties: 228 ethernet-ports: 229 patternProperties: 230 "^port@[3-8]$": false 231 "^port@[1-2]$": 232 properties: 233 reg: 234 minimum: 1 235 maximum: 2 236 237additionalProperties: false 238 239examples: 240 - | 241 #include <dt-bindings/soc/ti,sci_pm_domain.h> 242 #include <dt-bindings/net/ti-dp83867.h> 243 #include <dt-bindings/interrupt-controller/irq.h> 244 #include <dt-bindings/interrupt-controller/arm-gic.h> 245 246 bus { 247 #address-cells = <2>; 248 #size-cells = <2>; 249 250 mcu_cpsw: ethernet@46000000 { 251 compatible = "ti,am654-cpsw-nuss"; 252 #address-cells = <2>; 253 #size-cells = <2>; 254 reg = <0x0 0x46000000 0x0 0x200000>; 255 reg-names = "cpsw_nuss"; 256 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 257 dma-coherent; 258 clocks = <&k3_clks 5 10>; 259 clock-names = "fck"; 260 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 263 264 dmas = <&mcu_udmap 0xf000>, 265 <&mcu_udmap 0xf001>, 266 <&mcu_udmap 0xf002>, 267 <&mcu_udmap 0xf003>, 268 <&mcu_udmap 0xf004>, 269 <&mcu_udmap 0xf005>, 270 <&mcu_udmap 0xf006>, 271 <&mcu_udmap 0xf007>, 272 <&mcu_udmap 0x7000>; 273 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 274 "rx"; 275 276 ethernet-ports { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 280 cpsw_port1: port@1 { 281 reg = <1>; 282 ti,mac-only; 283 label = "port1"; 284 ti,syscon-efuse = <&mcu_conf 0x200>; 285 phys = <&phy_gmii_sel 1>; 286 287 phy-mode = "rgmii-id"; 288 phy-handle = <&phy0>; 289 }; 290 }; 291 292 davinci_mdio: mdio@f00 { 293 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 294 reg = <0x0 0xf00 0x0 0x100>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clocks = <&k3_clks 5 10>; 298 clock-names = "fck"; 299 bus_freq = <1000000>; 300 301 phy0: ethernet-phy@0 { 302 reg = <0>; 303 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 304 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 305 }; 306 }; 307 308 cpts@3d000 { 309 compatible = "ti,am65-cpts"; 310 reg = <0x0 0x3d000 0x0 0x400>; 311 clocks = <&k3_clks 18 2>; 312 clock-names = "cpts"; 313 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "cpts"; 315 ti,cpts-ext-ts-inputs = <4>; 316 ti,cpts-periodic-outputs = <2>; 317 }; 318 }; 319 }; 320