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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.txt6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,mt8186-fhctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek frequency hopping and spread spectrum clocking control
10 - Edward-JW Yang <edward-jw.yang@mediatek.com>
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
20 - mediatek,mt6795-fhctl
21 - mediatek,mt8173-fhctl
22 - mediatek,mt8186-fhctl
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H A Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dnuvoton,ma35d1-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chi-Fang Li <cfli0@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
18 include/dt-bindings/clock/ma35d1-clk.h
23 - const: nuvoton,ma35d1-clk
28 "#clock-cells":
34 nuvoton,pll-mode:
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dimx-sata.txt7 - compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10 - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
11 - interrupts : interrupt mapping for SATA IRQ
12 - reg : registers mapping
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names
15 - clock-names : should include "sata", "sata_ref" and "ahb" entries
18 - fsl,transmit-level-mV : transmit voltage level, in millivolts.
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H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
31 - description: sata clock
32 - description: sata reference clock
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/freebsd/sys/dev/isci/scil/
H A Dscu_bios_definitions.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
64 * stand-alone where the library is excluded. By excluding
208 * in APC mode, if ANY of the phy mask is non-zero,
230 * Spread Spectrum Clocking (SSC) setting for Tx:
306 * Operational Note: The following Look-Up-Table registers are engaged
308 * - Software programs the Link Layer AFE Look Up Table Control
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/freebsd/sys/arm64/rockchip/
H A Drk3568_combphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
57 {"rockchip,rk3568-naneng-combphy", 1},
174 switch (sc->mode) { in rk3568_combphy_enable()
179 bus_write_4(sc->mem, PHYREG7, in rk3568_combphy_enable()
183 bus_write_4(sc->mem, PHYREG15, in rk3568_combphy_enable()
184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
187 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, in rk3568_combphy_enable()
190 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2, in rk3568_combphy_enable()
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/freebsd/sys/arm/freescale/vybrid/
H A Dvf_anadig.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
58 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */
77 #define ANADIG_PLL1_SS 0x280 /* PLL1 Spread Spectrum */
112 { -1, 0 }
122 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig")) in anadig_probe()
183 if (bus_alloc_resources(dev, anadig_spec, sc->res)) { in anadig_attach()
189 sc->bst = rman_get_bustag(sc->res[0]); in anadig_attach()
190 sc->bsh = rman_get_bushandle(sc->res[0]); in anadig_attach()
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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H A Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-cubox-i.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-brcm.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
57 fsl,transmit-atten-16ths = <9>;
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H A Dimx6q-cubox-i-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad (1.5som)";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
57 fsl,transmit-atten-16ths = <9>;
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H A Dimx6q-cubox-i-emmc-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-sr-som-emmc.dtsi"
47 #include "imx6qdl-cubox-i.dtsi"
50 model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)";
51 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
56 fsl,transmit-level-mV = <1104>;
57 fsl,transmit-boost-mdB = <0>;
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H A Dimx6q-hummingboard2-emmc-som-v15.dts3 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
6 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
47 #include "imx6qdl-sr-som.dtsi"
48 #include "imx6qdl-sr-som-emmc.dtsi"
49 #include "imx6qdl-sr-som-ti.dtsi"
50 #include "imx6qdl-hummingboard2.dtsi"
59 fsl,transmit-level-mV = <1104>;
60 fsl,transmit-boost-mdB = <0>;
61 fsl,transmit-atten-16ths = <9>;
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H A Dimx6q-hummingboard2.dts2 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
5 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
47 #include "imx6qdl-hummingboard2.dtsi"
48 #include "imx6qdl-hummingboard2-emmc.dtsi"
57 fsl,transmit-level-mV = <1104>;
58 fsl,transmit-boost-mdB = <0>;
59 fsl,transmit-atten-16ths = <9>;
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H A Dimx6q-hummingboard2-som-v15.dts3 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
6 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
47 #include "imx6qdl-sr-som.dtsi"
48 #include "imx6qdl-sr-som-ti.dtsi"
49 #include "imx6qdl-hummingboard2.dtsi"
58 fsl,transmit-level-mV = <1104>;
59 fsl,transmit-boost-mdB = <0>;
60 fsl,transmit-atten-16ths = <9>;
61 fsl,no-spread-spectrum;
H A Dimx6q-dms-ba16.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx6q-ba16.dtsi"
9 model = "Advantech DMS-BA16";
10 compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba1
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drenesas,raa215300.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The RAA215300 is a high-performance, low-cost 9-channel PMIC designed for
14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
16 built-in Real-Time Clock (RTC), 32kHz crystal oscillator, and coin cell
18 ideal for System-On-Module (SOM) applications. A spread spectrum feature
19 provides an ease-of-use solution for noise-sensitive audio or RF applications.
25 …-power-management/multi-channel-power-management-ics-pmics/ssdsoc-power-management-ics-pmic-and-pm…
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pci
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
137 PLLDP: Clock source for eDP/LVDS (spread spectrum)
355 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
365 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
417 RD4(sc, sc->base_reg, &reg); in pll_enable()
418 if (sc->type != PLL_E) in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
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