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/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-spin-table.dtsi4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
[all …]
H A Dfoundation-v8.dts1 // SPDX-License-Identifier: GPL-2.0
8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv2.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
H A Dfoundation-v8-gicv3.dts1 // SPDX-License-Identifier: GPL-2.0
8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv3.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_mocs.c1 // SPDX-License-Identifier: MIT
17 struct drm_i915_mocs_table table; member
33 ce->ring_size = SZ_16K; in mocs_context_create()
43 err = -ETIME; in request_add_sync()
49 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
55 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
56 err = -ETIME; in request_add_spin()
69 flags = get_mocs_settings(gt->i915, &arg->table); in live_mocs_init()
71 return -EINVAL; in live_mocs_init()
74 arg->l3cc = &arg->table; in live_mocs_init()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
23 #address-cells = <2>;
[all …]
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992-lg-h815.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
16 /delete-node/ &cont_splash_mem;
19 /delete-node/ &dfps_data_mem;
24 chassis-type = "handset";
26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
31 /delete-node/ psci;
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
15 cpu-release-addr = /bits/ 64 <0>;
19 enable-method = "spin-table";
20 cpu-release-addr = /bits/ 64 <0>;
/linux/drivers/clk/stm32/
H A Dclk-stm32-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
7 #include <linux/clk-provider.h>
16 u32 *table; member
32 const struct clk_div_table *table; member
95 spinlock_t *lock; /* spin lock */
105 spinlock_t *lock; /* spin lock */
115 spinlock_t *lock; /* spin lock */
127 spinlock_t *lock; /* spin lock */
/linux/Documentation/hwmon/
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
/linux/kernel/locking/
H A Dqspinlock_paravirt.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
17 * pv_kick(cpu) -- wakes a suspended vcpu
31 * mitigates the slight slowdown for non-overcommitted guest with this
32 * aggressive wait-early mechanism.
64 * pv_wait_head_or_lock() to signal that it is ready to spin on the lock.
88 int val = atomic_read(&lock->val); in pv_hybrid_queued_unfair_trylock()
92 try_cmpxchg_acquire(&lock->locked, &old, _Q_LOCKED_VAL)) { in pv_hybrid_queued_unfair_trylock()
112 WRITE_ONCE(lock->pending, 1); in set_pending()
124 return !READ_ONCE(lock->locked) && in trylock_clear_pending()
[all …]
/linux/arch/arm64/kernel/
H A Dsmp_spin_table.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spin Table SMP initialisation
50 return -ENODEV; in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
72 return -ENODEV; in smp_spin_table_cpu_prepare()
75 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare()
83 return -ENOMEM; in smp_spin_table_cpu_prepare()
87 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare()
89 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare()
[all …]
/linux/arch/powerpc/platforms/44x/
H A Diss4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
12 * Copyright (c) 2003-2005 Zultys Technologies
54 for_each_node_with_property(np, "interrupt-controller") { in iss4xx_init_irq()
66 } else if (of_device_is_compatible(np, "chrp,open-pic")) { in iss4xx_init_irq()
68 * device-tree, just pass 0 to all arguments in iss4xx_init_irq()
94 /* Assume spin table. We could test for the enable-method in in smp_iss4xx_kick_cpu()
95 * the device-tree but currently there's little point as it's in smp_iss4xx_kick_cpu()
98 spin_table_addr_prop = of_get_property(cpunode, "cpu-release-addr", in smp_iss4xx_kick_cpu()
101 pr_err("CPU%d: Can't start, missing cpu-release-addr !\n", cpu); in smp_iss4xx_kick_cpu()
[all …]
H A Dppc476.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright 2002-2005 MontaVista Software Inc.
13 * Copyright (c) 2003-2005 Zultys Technologies
98 { "akebono-avr" },
104 .name = "akebono-avr",
125 for_each_node_with_property(np, "interrupt-controller") { in ppc47x_init_irq()
133 if (of_device_is_compatible(np, "chrp,open-pic")) { in ppc47x_init_irq()
135 * device-tree, just pass 0 to all arguments in ppc47x_init_irq()
163 /* Assume spin table. We could test for the enable-method in in smp_ppc47x_kick_cpu()
164 * the device-tree but currently there's little point as it's in smp_ppc47x_kick_cpu()
[all …]
/linux/kernel/bpf/
H A Drqspinlock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Resilient Queued Spin Lock
5 * (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
6 * (C) Copyright 2013-2014,2018 Red Hat, Inc.
8 * (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
9 * (C) Copyright 2024-2025 Meta Platforms, Inc. and affiliates.
44 * The basic principle of a queue-based spinlock can best be understood
45 * by studying a classic queue-based spinlock implementation called the
47 * Synchronization on Shared-Memory Multiprocessors by Mellor-Crummey and
58 * unlock the next pending (next->locked), we compress both these: {tail,
[all …]
/linux/arch/arm64/boot/dts/axiado/
H A Dax3000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
14 interrupt-parent = <&gic500>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
[all …]
/linux/Documentation/kernel-hacking/
H A Dlocking.rst35 .. table:: Expected Results
37 +------------------------------------+------------------------------------+
41 +------------------------------------+------------------------------------+
43 +------------------------------------+------------------------------------+
45 +------------------------------------+------------------------------------+
47 +------------------------------------+------------------------------------+
49 +------------------------------------+------------------------------------+
51 +------------------------------------+------------------------------------+
55 .. table:: Possible Results
57 +------------------------------------+------------------------------------+
[all …]
/linux/net/tipc/
H A Dnet.c4 * Copyright (c) 1995-2006, 2014, Ericsson AB
5 * Copyright (c) 2005, 2010-2011, Wind River Systems
71 * are protected by node spin lock.
79 * - The tipc_port spin_lock. This is protecting each port instance
82 * corresponding reference table entry, which has the same life
85 * been added in the port instance, -to be used for unlocking
87 * - A read/write lock to protect the reference table itself (teg.c).
88 * (Nobody is using read-only access to this, so it can just as
90 * - A spin lock to protect the registry of kernel/driver users (reg.c)
91 * - A global spin_lock (tipc_port_lock), which only task is to ensure
[all …]
/linux/arch/powerpc/kernel/
H A Dsetup_64.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 #include <asm/asm-prototypes.h>
63 #include <asm/text-patching.h>
68 #include <asm/feature-fixups.h>
101 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
108 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
127 /* Look for ibm,smt-enabled OF option */
151 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
166 /* Look for smt-enabled= cmdline option */
172 early_param("smt-enabled", early_smt_enabled);
[all …]

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